ch_fifo.mrp

it describe how to develop the field programmable gate array

Release 5.1i - Map F.22
Xilinx Mapping Report File for Design 'ch_fifo'

Design Information
------------------
Command Line   : Y:/XILI/QualityPartnerBuild3/bin/nt/map.exe -quiet -p
xc2v40-fg256-4 -cm area -pr b -k 4 -c 100 -tx off -o ch_fifo_map.ncd ch_fifo.ngd
ch_fifo.pcf 
Target Device  : x2v40
Target Package : fg256
Target Speed   : -4
Mapper Version : virtex2 -- $Revision: 1.4 $
Mapped Date    : Thu Jul 11 16:51:50 2002

Design Summary
--------------
   Number of errors:      0
   Number of warnings:    0
   Number of Slices:                   69 out of     256   26%
   Number of Slices containing
      unrelated logic:                  0 out of      69    0%
   Number of Slice Flip Flops:         78 out of     512   15%
   Total Number 4 input LUTs:         103 out of     512   20%
      Number used as LUTs:                           94
      Number used as a route-thru:                    9
   Number of bonded IOBs:              17 out of      88   19%
      IOB Flip Flops:                                 5
   Number of Block RAMs:                1 out of       4   25%
   Number of GCLKs:                     2 out of      16   12%
   Number of DCMs:                      1 out of       4   25%
Total equivalent gate count for design:  74,025
Additional JTAG gate count for IOBs:  816
Peak Memory Usage:  52 MB

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------

Section 3 - Informational
-------------------------
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFG symbol "MyDCM_inst_CLK0_BUFG_INST" (output signal=wr_clk),
   BUFG symbol "MyDCM_inst_CLK2X_BUFG_INST" (output signal=rd_clk)
INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| almost_empty                       | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OFF1     |          |       |
| almost_full                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OFF1     |          |       |
| data_ch                            | IOB     | INPUT     | LVTTL       |          |      | INFF1    |          |       |
| empty                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OFF1     |          |       |
| full                               | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OFF1     |          |       |
| pn_lock_rd_clk                     | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rd                                 | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| rd_data<0>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rd_data<1>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rd_data<2>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rd_data<3>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rd_data<4>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rd_data<5>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rd_data<6>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rd_data<7>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| reset                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| wr_clk_in                          | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.