⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 ch_fifo_preroute.twr

📁 it describe how to develop the field programmable gate array
💻 TWR
字号:
--------------------------------------------------------------------------------
Release 5.1i - Trace F.22
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Y:/XILI/QualityPartnerBuild3/bin/nt/trce.exe -quiet -e 3 -l 3 -s -4 -xml
ch_fifo_preroute ch_fifo_map.ncd -o ch_fifo_preroute.twr ch_fifo.pcf

Design file:              ch_fifo_map.ncd
Physical constraint file: ch_fifo.pcf
Device,speed:             xc2v40,-4 (ADVANCED 1.108 2002-06-12, STEPPING level 1)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock wr_clk_in
---------------+------------+------------+
               |  Setup to  |  Hold to   |
Source Pad     | clk (edge) | clk (edge) |
---------------+------------+------------+
data_ch        |    1.938(R)|   -1.717(R)|
rd             |    3.004(R)|   -2.447(R)|
reset          |    3.458(R)|   -3.043(R)|
---------------+------------+------------+

Clock wr_clk_in to Pad
---------------+------------+
               | clk (edge) |
Destination Pad|   to PAD   |
---------------+------------+
almost_empty   |    5.582(R)|
almost_full    |    5.582(R)|
empty          |    5.582(R)|
full           |    5.582(R)|
pn_lock_rd_clk |    5.841(R)|
rd_data<0>     |    7.920(R)|
rd_data<1>     |    7.920(R)|
rd_data<2>     |    7.920(R)|
rd_data<3>     |    7.920(R)|
rd_data<4>     |    7.920(R)|
rd_data<5>     |    7.920(R)|
rd_data<6>     |    7.920(R)|
rd_data<7>     |    7.920(R)|
---------------+------------+

Clock to Setup on destination clock wr_clk_in
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
wr_clk_in      |    4.593|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Thu Jul 11 16:53:00 2002
--------------------------------------------------------------------------------

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -