uart.s

一个可以驱动 onenand的代码,使用ADS编译

;;-----------------------------------------------------------------------
;; 2006.9 by lihan  (aoxun electronics teclnology hardware dep)
;; This program can write data (length is decide by PC program)from PC RS232 to SDRAM 0xA0000000 
;; it will jump to 0xa0000000 when write finished
;;-----------------------------------------------------------------------

PSSR_PH              EQU    (0x1 << 4)|(0x1 << 5)
PSSR_PHYSICAL	     EQU    (0x40F00004)

CKEN_PHYSICAL        EQU    0x41300004
CKEN_BTUART          EQU    (0x1 << 7)

OSCR_PHYSICAL	     EQU    (0x40A00010)

xlli_GPIOREGS_PHYSICAL_BASE	 EQU 	0x40E00000

xlli_GPLR0_offset    EQU    (0x000)  ; GPIO Level registers
xlli_GPLR1_offset    EQU    (0x004)
xlli_GPLR2_offset    EQU    (0x008)
xlli_GPLR3_offset    EQU    (0x100)

xlli_GPDR0_offset    EQU    (0x00C)  ; GPIO Direction registers
xlli_GPDR1_offset    EQU    (0x010)
xlli_GPDR2_offset    EQU    (0x014)
xlli_GPDR3_offset    EQU    (0x10C)

xlli_GPSR0_offset    EQU    (0x018)  ; GPIO Set registers
xlli_GPSR1_offset    EQU    (0x01C)
xlli_GPSR2_offset    EQU    (0x020)
xlli_GPSR3_offset    EQU    (0x118)

xlli_GPCR0_offset    EQU    (0x024)  ; GPIO Clear registers
xlli_GPCR1_offset    EQU    (0x028)
xlli_GPCR2_offset    EQU    (0x02C)
xlli_GPCR3_offset    EQU    (0x124)

xlli_GAFR0_L_offset  EQU    (0x054)  ; GPIO Alternate function registers (Bits 15:0)
xlli_GAFR0_U_offset  EQU    (0x058)  ; Bits 31:16
xlli_GAFR1_L_offset  EQU    (0x05c)  ; Bits 47:32
xlli_GAFR1_U_offset  EQU    (0x060)  ; Bits 63:48
xlli_GAFR2_L_offset  EQU    (0x064)  ; Bits 79:64
xlli_GAFR2_U_offset  EQU    (0x068)  ; Bits 95:80
xlli_GAFR3_L_offset  EQU    (0x06C)  ; Bits 111:96
xlli_GAFR3_U_offset  EQU    (0x070)  ; Bits 127:112

FFUART_PHYSICAL_BASE    EQU    0x40100000   ; Full Featured UART base address
BTUART_PHYSICAL_BASE    EQU    0x40200000   ; BlueTooth UART base address
STUART_PHYSICAL_BASE    EQU    0x40700000   ; Standard UART base address   
   
UARBR_offset     EQU     (0X0)   ; UART Receive Buffer Register offset
UATHR_offset	 EQU     (0X0)   ; UART Transmit Holding Register offset
UAIER_offset	 EQU     (0x4)   ; UART Interrupt Enable Register offset
UAIIR_offset	 EQU     (0x8)   ; UART Interrupt ID Register offset
UAFCR_offset	 EQU     (0x8)   ; UART FIFO Control Register offset
UALCR_offset	 EQU     (0xC)   ; UART Line Control Register offset
UAMCR_offset	 EQU     (0x10)  ; UART Modem Control Register offset
UALSR_offset	 EQU     (0x14)  ; UART Line Status Register offset
UAMSR_offset	 EQU     (0x18)  ; UART Modem Status Register offset
UASPR_offset	 EQU     (0x1C)  ; UART Scratch Pad Register offset
UADLL_offset	 EQU     (0x0)   ; UART Divisor Latch Register (low) offset
UADLH_offset	 EQU     (0X4)   ; UART Divisor Latch Register (high) offset
UAISR_offset	 EQU     (0x20)  ; UART Slow Infrared Selector Register offset 
  
UART_TDRQ     EQU     (0x20)   ; Transmit Data Request
UART_TEMT     EQU     (0x40)   ; Transmitter Empty bit
UART_DR       EQU     (0x01)   ; Data Ready bit
UART_DLAB	  EQU     (0x80)   ; DLAB bit
UART_nBT_OFF  EQU     (0x100)  ; BTUART Tranceiver Control Bit
UART_BTDTR    EQU     (0x80)   ; BTUART Data Terminal Ready bit


   AREA  |text|,CODE,READONLY 
   
   EXPORT  UART_Loop
   
 
UART_getchr FUNCTION

              
11      ldr    r1,  [r0, #UALSR_offset]      ; Get Line Status Register Data
        ands   r1,  r1,  #UART_DR                 ; Is the data ready bit set?
        beq   %b11                           ; No - return to caller with 0x00 in r2
        
        ldr    r2,  [r0, #UARBR_offset]      ; Fetch byte out of receive buffer
        ;mov   r2,  r1
        
        mov     pc,     lr      ; Otherwise - return to caller 
        
        ENDFUNC     
        
UART_putchr   FUNCTION

12
        ldr    r1,  [r0, #UALSR_offset]      ; Get Line Status Register Data
        ands   r1,  r1,  #UART_TDRQ               ; Is TDRQ (Transmit Data Request) bit set?
        beq    %B12                               ; No - loop until it is
        strb   r2,  [r0, #UATHR_offset]      ; It's ready! - output byte to buffer	
        mov    pc,  lr                           ; Return to caller

        ENDFUNC          

UART_Loop 
      ;;************************uart init************************************
      ;; step 1,2,3 can cut if memset-bvd.s have do same 

      ;;Step 1:   Enable STDUART clock in cken register    
        ;ldr     r1,  =CKEN_PHYSICAL;  ; CKEN addr 
        ;ldr     r2,[r1]
        ;orr     r2,  r2,#CKEN_STDUART ;cken[7], STDuart clock , can add CKEN5_STUART in cken memset-bvd.s     
        ;str     r2,  [r1]      ;                          ; 
 

      ;;Step 2:   GPIO config ,direct,Fn **********GPIO46 STDRXD ;  GPIO47:STDTXD;             
        ldr     r0,  =xlli_GPIOREGS_PHYSICAL_BASE  ; Get the GPIO registers base address        
        ldr     r1,  =0x00008000;  ; Get the GPIO registers base address        
        str     r1,  [r0, #xlli_GPDR1_offset]      ; 
        ldr     r1,  =0x60000000;  ; Get the GPIO registers base address        
        str     r1,  [r0, #xlli_GAFR1_L_offset]      ;      

      ;;Step 3:   set PSSR PH bit for enable all GPIO work          
 	ldr		r0,	=PSSR_PHYSICAL
	ldr		r1,	=PSSR_PH
	str		r1, [r0]        
      ;;Step 4:   OS-timer must enable for delay  

        ldr    r0,  =STUART_PHYSICAL_BASE
        mov    r1,  #0x0                         ; Zero out a work register
        ;next 6 instruction can cut for default config
        ;str    r1,  [r0, #UAIER_offset]      ; Zero out Interrupt Enable Register
        ;str    r1,  [r0, #UAFCR_offset]      ; Zero out FIFO Control Register
        ;str    r1,  [r0, #UALCR_offset]      ; Zero out Line Control Register
        ;str    r1,  [r0, #UAMCR_offset]      ; Zero out Modem Control Register
        ;str    r1,  [r0, #UAISR_offset]      ; Zero out IR bit register
        ;ldr    r1,  [r0, #UAMSR_offset]      ; Read MSR once to clear bits

        mov    r1,  #0x87                  ;7: 8N2      ; Set up divisor latch bit (DLAB), 8 bit character, no parity, 1 stop bit
        str    r1,  [r0,  #UALCR_offset]     ; Set DLAB bit

        mov    r2,  #0x8    ;; 14745600/(16*baud)=115200;
        str    r2,  [r0,  #UADLL_offset]     ; set baud rate
        ldr    r1,  =0x0                         ; Insure high baud rate byte is zero
        str    r1,  [r0,  #UADLH_offset]

        
        ldr    r1,  [r0,  #UALCR_offset]     ; Get LCR values
        bic    r1,  r1,   #UART_DLAB              ; Clear DLAB bit
        str    r1,  [r0,  #UALCR_offset]     ; Write the value back out
        mov    r1,  #0x07                        ; This value will clear the TX and RX FIFOs
        str    r1,  [r0,  #UAFCR_offset]     ; ... and enabale the FIFOs for use.

        mov    r1,  #0x40                        ; set unit enable bit
        str    r1,  [r0,  #UAIER_offset]     ; enable the UART
        
        
       

         ldr r3, =OSCR_PHYSICAL   ;approx. 3.25MHz OS time base 
	 ldr r4, [r3] 
	 add r2,r4,#0x8000    ;approx. 40ms=3,250*40 tick=0x1FBD0  approx 0.7ms/Bytes use 115200kbps 
	 
14       ldr    r1,  [r0, #UALSR_offset]      ; Get Line Status Register Data
         ands   r1,  r1,  #UART_DR                 ; Is the data ready bit set?         
         bne   %f16                           ; No - return to caller with 0x00 in r2 
	 
	 ldr r4, [r3]
	 cmp r2, r4
	 bgt %b14                             ; Branch if Greater than or Equal
	 b   %f19 

	 
	        
             
16       ldr    r2,  [r0, #UARBR_offset]      ; Fetch byte out of receive buffer
         
         cmp     r2,     #0x45    ; Was it a 'E'        
         bne     %f19 
         
         mov    r2,#0x43   ;send ACK 'C'
         bl     UART_putchr        
         
       
17       bl     UART_getchr
         cmp     r2,     #0x6A    ; Start ram 'j'
         bne     %b17  


         mov    r3, #0x0
         bl     UART_getchr         
         add     r3, r3,   r2    ;ram lentgth
         
         bl     UART_getchr
         add     r3, r3, r2 ,lsl#8    
                
         bl     UART_getchr
         add     r3, r3, r2 ,lsl#16        
         
          
         bl     UART_getchr       
         add     r3, r3, r2 ,lsl#24        
         
         ldr r4,=0xa0000000;
         add     r3, r3  ,r4 
                      
18       bl     UART_getchr
         strb r2, [r4]
         add r4,r4,#1
         
         cmp r3,r4
         bne   %b18 
         
         ldr pc,=0xa0000000                 

19       mov    pc,  lr                         ; Return to caller

        
            
 END