onbl1.s

一个可以驱动 onenand的代码,使用ADS编译

 ;=========================================
 ; NAME: Init.S
 ; DESC: Configure memory, ISR ,stacks
 ;       Initialize C-variables
 ; HISTORY:
 ;=========================================

;.include "Startup/pxa-regs.inc"






	AREA	startup, code, readonly
    IMPORT  read
    IMPORT UART_Loop
  
   	EXPORT  StartUp
   
    
StartUp 
    ENTRY
	B	ResetHandler  
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
   
 ;-----------------------------------
 ; Steppingstone loader entry point.
 ;-----------------------------------
ResetHandler
	ldr     r0, =0x40F00030
    ldr     r6, [r0]
    
		ldr 	r0,	=0xD3		 ; 0x13 (SVC), 0xC0(NoIntsMask)
	msr	cpsr_c, r0
	ldr 	r0,	=0x2043
	mcr	p15,0,r0,c15,c1,0



	

;        /* ---------------------------------------------------------------- */
;        /* Disable (mask) all interrupts at interrupt controller            */
;        /* ---------------------------------------------------------------- */
initirqs

        mov     r1,  #0        ; /* clear int. level register (IRQ, not FIQ) */
        ldr     r2,  =0x40D00008
        str     r1,  [r2]

        ldr     r2,  =0x40D000A0     ; /* mask all interrupts at the controller    */
        str     r1,  [r2]

;        /* ---------------------------------------------------------------- */
;        /* I cache D cache enable                                           */
;	/* ---------------------------------------------------------------- */
	ldr	r1, =0x1004
	mrc p15,0,r0,c1,c0,0
	orr r0,r0,r1
	mcr p15,0,r0,c1,c0,0



;        /* ---------------------------------------------------------------- */
;        /* Clock initialisation                                             */
;        /* ---------------------------------------------------------------- */
initclks
 ;       /* Disable the peripheral clocks, and set the core clock frequency  */

  ;      /* Turn Off on-chip peripheral clocks (except for memory)           */
   ;     /* for re-configuration.                                            */
        ldr     r1,  =0x41300004
        ldr     r2,  =0x00400220  ;//打开串口时钟
        str     r2,  [r1]

   ;     /* ... and write the core clock config register                     */
        ldr     r2,  =0x02000290
        ldr     r1,  =0x41300000
        str     r2,  [r1]

    ;    /* Turn on turbo mode */
        mrc     p14, 0, r2, c6, c0, 0
        orr     r2, r2, #0xB           ; /* Turbo, Fast-Bus, Freq change**/
        mcr     p14, 0, r2, c6, c0, 0
	
	ldr	r1, =0x48000000
	ldr	r2, =0x7ff0fff9	
	str	r2, [r1, #0x8]
	
	;ldr	r2, =0x0000a691
	;str	r2, [r1, #0xc]

	;ldr	r2, =0x0000b884 
	;str	r2, [r1, #0x10]

	;ldr	r2, =0x00000001 
	;str	r2, [r1, #0x14]

	;ldr	r2, =0x00010204 
	;str	r2, [r1, #0x28]
	
	;ldr     r2, =0x00010204 
    ;str     r2, [r1, #0x2c]

       ;ldr     r2, =0x00010204 
        ;str     r2, [r1, #0x30]

        ;ldr     r2, =0x00010204
       ; str     r2, [r1, #0x34]

        ;ldr     r2, =0x0000c108 
       ; str     r2, [r1, #0x38]

       ;ldr     r2, =0x0001c108 
       ;str     r2, [r1, #0x3C]

        ;        ldr     r2, =0x20ca2018 
        ;str     r2, [r1, #0x4]

        ;ldr     r2, =0x20cb2018 
        ;str     r2, [r1, #0x4]

        ;ldr     r2, =0x208b2018 
        ;str     r2, [r1, #0x4]

        ldr     r2, =0x208ba018	
        str     r2, [r1, #0x4]

	    ldr     r2, =0x00000ac8 
        str     r2, [r1, #0x0]

	
      ; /* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
      ; /*          100..200 .ec.                                          */
      ; /* The sequence below is based on the recommended init steps detailed */
      ; /* in the Intel PXA255 Processor Developer's Manual Section 6.11 */

       ldr r3, =0x40A00010                   ;/* reset the OS Timer Count to zero */
       mov r2, #0
       str r2, [r3]
       ldr r4, =0x300                  ;/* really 0x2E1 is about 200usec,   */
                                      ; /* so 0x300 should be plenty        */
nand5
    ldr r2, [r3]
    cmp r4, r2
    bgt nand5

       ;/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
       ;/*          attempting non-burst read or write accesses to disabled */
       ;/*          SDRAM, as commonly specified in the power up sequence   */
       ;/*          documented in SDRAM data sheets. The address(es) used   */
      ; /*          for this purpose must not be cacheable.                 */

       ldr     r3,     =0xa0000000
       str     r2,     [r3]
       str     r2,     [r3]
       str     r2,     [r3]
       str     r2,     [r3]
       str     r2,     [r3]
       str     r2,     [r3]
       str     r2,     [r3]
       str     r2,     [r3]


      ; /* Step 4g: Write MDCNFG with enable bits asserted  */
       ;/* (MDCNFG:DEx set to 1). */
	ldr	r3, =0x00000ac9
	str	r3, [r1, #0x0]

       ldr     r3,	[r1, #0x0]
       mov     r4, 	r3
       orr     r3,	r3,  #0x00000001
       str     r3,	[r1, #0x0]
       mov     r0, 	r3

      ; /* Step 4h: Write MDMRS. */

       ldr     r2,  =0x00000000 
       str     r2,  [r1, #0x40]

	ldr	r3, = 0x209ba018
	str	r3, [r1, #0x4]

       ;/* enable APD */
       ldr     r3,  [r1, #0x4]
       orr     r3,  r3,  #(1 << 20)
       str     r3,  [r1, #0x4]

       ;/* We are finished with Intel's memory controller initialisation    */

        
	;/* Interrupt init: Mask all interrupts                              */
	ldr 	r0, =0x40D00004 ;/* enable no sources */
        mov 	r1, #0
	str 	r1, [r0]

		tst r6, #4
		beq tag0
		ldrne r0, =0x40F00008
	;/* add keypad_light */
		
		mov     r1,  #0x080000                                          
        ldr     r2,  =0x40E0000C ;GPDR0 
        str     r1,  [r2]

        ldr     r2,  =0x40e00018
        str     r1,  [r2]


       	ldrne r1, [r0]
       	movne pc, r1
tag0	
        ldr     sp,=0xA2f00000     
        bl      UART_Loop
        b      read