pxa-regs.inc

一个可以驱动 onenand的代码,使用ADS编译

.equ	 PCFR_DS,	(1 << 3)	/* Deep Sleep Mode */
.equ	 PCFR_FS,	(1 << 2)	/* Float Static Chip Selects */
.equ	 PCFR_FP,	(1 << 1)	/* Float PCMCIA controls */
.equ	 PCFR_OPDE,	(1 << 0)	/* 3.6864 MHz oscillator power-down enable */

.equ	 RCSR_GPR,	(1 << 3)	/* GPIO Reset */
.equ	 RCSR_SMR,	(1 << 2)	/* Sleep Mode */
.equ	 RCSR_WDR,	(1 << 1)	/* Watchdog Reset */
.equ	 RCSR_HWR,	(1 << 0)	/* Hardware Reset */

/*
 * SSP Serial Port Registers
 */
.equ	 SSCR0,		(0x41000000)  /* SSP Control Register 0 */
.equ	 SSCR1,		(0x41000004)  /* SSP Control Register 1 */
.equ	 SSSR,		(0x41000008)  /* SSP Status Register */
.equ	 SSITR,		(0x4100000C)  /* SSP Interrupt Test Register */
.equ	 SSDR,		(0x41000010)  /* (Write / Read) SSP Data Write Register/SSP Data Read Register */

/*
 * MultiMediaCard (MMC) controller
 */
.equ	 MMC_STRPCL,	(0x41100000)  /* Control to start and stop MMC clock */
.equ	 MMC_STAT,	(0x41100004)  /* MMC Status Register (read only) */
.equ	 MMC_CLKRT,	(0x41100008)  /* MMC clock rate */
.equ	 MMC_SPI,	(0x4110000c)  /* SPI mode control bits */
.equ	 MMC_CMDAT,	(0x41100010)  /* Command/response/data .equ	ence control */
.equ	 MMC_RESTO,	(0x41100014)  /* Expected response time out */
.equ	 MMC_RDTO,	(0x41100018)  /* Expected data read time out */
.equ	 MMC_BLKLEN,	(0x4110001c)  /* Block length of data transaction */
.equ	 MMC_NOB,	(0x41100020)  /* Number of blocks, for block mode */
.equ	 MMC_PRTBUF,	(0x41100024)  /* Partial MMC_TXFIFO FIFO written */
.equ	 MMC_I_MASK,	(0x41100028)  /* Interrupt Mask */
.equ	 MMC_I_REG,	(0x4110002c)  /* Interrupt Register (read only) */
.equ	 MMC_CMD,	(0x41100030)  /* Index of current command */
.equ	 MMC_ARGH,	(0x41100034)  /* MSW part of the current command argument */
.equ	 MMC_ARGL,	(0x41100038)  /* LSW part of the current command argument */
.equ	 MMC_RES,	(0x4110003c)  /* Response FIFO (read only) */
.equ	 MMC_RXFIFO,	(0x41100040)  /* Receive FIFO (read only) */
.equ	 MMC_TXFIFO,	(0x41100044)  /* Transmit FIFO (write only) */

/*
 * Core Clock
 */
.equ	 CCCR,		(0x41300000)  /* Core Clock Configuration Register */
.equ	 CKEN,		(0x41300004)  /* Clock Enable Register */
.equ	 OSCC,		(0x41300008)  /* Oscillator Configuration Register */

.equ	 CCCR_N_MASK,	0x0380		/* Run Mode F.equ	ency to Turbo Mode F.equ	ency Multiplier */
#if !defined(CONFIG_PXA27X)
.equ	 CCCR_M_MASK,	0x0060		/* Memory F.equ	ency to Run Mode F.equ	ency Multiplier */
#endif
.equ	 CCCR_L_MASK,	0x001f		/* Crystal F.equ	ency to Memory F.equ	ency Multiplier */

.equ	 CKEN24_CAMERA,	(1 << 24)	/* Camera Interface Clock Enable */
.equ	 CKEN23_SSP1,	(1 << 23)	/* SSP1 Unit Clock Enable */
.equ	 CKEN22_MEMC,	(1 << 22)	/* Memory Controller Clock Enable */
.equ	 CKEN21_MEMSTK,	(1 << 21)	/* Memory Stick Host Controller */
.equ	 CKEN20_IM,	(1 << 20)	/* Internal Memory Clock Enable */
.equ	 CKEN19_KEYPAD,	(1 << 19)	/* Keypad Interface Clock Enable */
.equ	 CKEN18_USIM,	(1 << 18)	/* USIM Unit Clock Enable */
.equ	 CKEN17_MSL,	(1 << 17)	/* MSL Unit Clock Enable */
.equ	 CKEN16_LCD,	(1 << 16)	/* LCD Unit Clock Enable */
.equ	 CKEN15_PWRI2C,	(1 << 15)	/* PWR I2C Unit Clock Enable */
.equ	 CKEN14_I2C,	(1 << 14)	/* I2C Unit Clock Enable */
.equ	 CKEN13_FICP,	(1 << 13)	/* FICP Unit Clock Enable */
.equ	 CKEN12_MMC,	(1 << 12)	/* MMC Unit Clock Enable */
.equ	 CKEN11_USB,	(1 << 11)	/* USB Unit Clock Enable */
#if defined(CONFIG_PXA27X)
.equ	 CKEN10_USBHOST,	(1 << 10)	/* USB Host Unit Clock Enable */
.equ	 CKEN24_CAMERA,	(1 << 24)	/* Camera Unit Clock Enable */
#endif
.equ	 CKEN8_I2S,	(1 << 8)	/* I2S Unit Clock Enable */
.equ	 CKEN7_BTUART,	(1 << 7)	/* BTUART Unit Clock Enable */
.equ	 CKEN6_FFUART,	(1 << 6)	/* FFUART Unit Clock Enable */
.equ	 CKEN5_STUART,	(1 << 5)	/* STUART Unit Clock Enable */
.equ	 CKEN3_SSP,	(1 << 3)	/* SSP Unit Clock Enable */
.equ	 CKEN2_AC97,	(1 << 2)	/* AC97 Unit Clock Enable */
.equ	 CKEN1_PWM1,	(1 << 1)	/* PWM1 Clock Enable */
.equ	 CKEN0_PWM0,	(1 << 0)	/* PWM0 Clock Enable */

.equ	 OSCC_OON,	(1 << 1)	/* 32.768kHz OON (write-once only bit) */
.equ	 OSCC_OOK,	(1 << 0)	/* 32.768kHz OOK (read-only bit) */

#if !defined(CONFIG_PXA27X)
.equ		 CCCR_L09,      (0x1F)
.equ		 CCCR_L27,      (0x1)
.equ		 CCCR_L32,      (0x2)
.equ		 CCCR_L36,      (0x3)
.equ		 CCCR_L40,      (0x4)
.equ		 CCCR_L45,      (0x5)

.equ		 CCCR_M1,       (0x1 << 5)
.equ		 CCCR_M2,       (0x2 << 5)
.equ		 CCCR_M4,       (0x3 << 5)

.equ		 CCCR_N10,      (0x2 << 7)
.equ		 CCCR_N15,      (0x3 << 7)
.equ		 CCCR_N20,      (0x4 << 7)
.equ		 CCCR_N25,      (0x5 << 7)
.equ		 CCCR_N30,      (0x6 << 7)
#endif

/*
 * LCD
 */
.equ	 LCCR0,		(0x44000000)  /* LCD Controller Control Register 0 */
.equ	 LCCR1,		(0x44000004)  /* LCD Controller Control Register 1 */
.equ	 LCCR2,		(0x44000008)  /* LCD Controller Control Register 2 */
.equ	 LCCR3,		(0x4400000C)  /* LCD Controller Control Register 3 */
.equ	 DFBR0,		(0x44000020)  /* DMA Channel 0 Frame Branch Register */
.equ	 DFBR1,		(0x44000024)  /* DMA Channel 1 Frame Branch Register */
.equ	 LCSR0,		(0x44000038)  /* LCD Controller Status Register */
.equ	 LCSR1,		(0x44000034)  /* LCD Controller Status Register */
.equ	 LIIDR,		(0x4400003C)  /* LCD Controller Interrupt ID Register */
.equ	 TMEDRGBR,	(0x44000040)  /* TMED RGB Seed Register */
.equ	 TMEDCR,	(0x44000044)  /* TMED Control Register */

.equ	 FDADR0,	(0x44000200)  /* DMA Channel 0 Frame Descriptor Address Register */
.equ	 FSADR0,	(0x44000204)  /* DMA Channel 0 Frame Source Address Register */
.equ	 FIDR0,		(0x44000208)  /* DMA Channel 0 Frame ID Register */
.equ	 LDCMD0,	(0x4400020C)  /* DMA Channel 0 Command Register */
.equ	 FDADR1,	(0x44000210)  /* DMA Channel 1 Frame Descriptor Address Register */
.equ	 FSADR1,	(0x44000214)  /* DMA Channel 1 Frame Source Address Register */
.equ	 FIDR1,		(0x44000218)  /* DMA Channel 1 Frame ID Register */
.equ	 LDCMD1,	(0x4400021C)  /* DMA Channel 1 Command Register */

.equ	 LCCR0_ENB,	(1 << 0)	/* LCD Controller enable */
.equ	 LCCR0_CMS,	(1 << 1)	/* Color = 0, Monochrome = 1 */
.equ	 LCCR0_SDS,	(1 << 2)	/* Single Panel = 0, Dual Panel = 1 */
.equ	 LCCR0_LDM,	(1 << 3)	/* LCD Disable Done Mask */
.equ	 LCCR0_SFM,	(1 << 4)	/* Start of frame mask */
.equ	 LCCR0_IUM,	(1 << 5)	/* Input FIFO underrun mask */
.equ	 LCCR0_EFM,	(1 << 6)	/* End of Frame mask */
.equ	 LCCR0_PAS,	(1 << 7)	/* Passive = 0, Active = 1 */
.equ	 LCCR0_BLE,	(1 << 8)	/* Little Endian = 0, Big Endian = 1 */
.equ	 LCCR0_DPD,	(1 << 9)	/* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */
.equ	 LCCR0_DIS,	(1 << 10)	/* LCD Disable */
.equ	 LCCR0_QDM,	(1 << 11)	/* LCD Quick Disable mask */
.equ	 LCCR0_PDD,	(0xff << 12)	/* Palette DMA .equ	est delay */
.equ	 LCCR0_PDD_S,	12
.equ	 LCCR0_BM,	(1 << 20)	/* Branch mask */
.equ	 LCCR0_OUM,	(1 << 21)	/* Output FIFO underrun mask */
.equ	 LCCR0_LCDT,	(1 << 22)	/* LCD Panel Type */
.equ	 LCCR0_RDSTM,	(1 << 23)	/* Read Status Interrupt Mask */
.equ	 LCCR0_CMDIM,	(1 << 24)	/* Command Interrupt Mask */


#if 0
.equ	 LCCR3_PCD,	(0xff)		/* Pixel clock divisor */
.equ	 LCCR3_ACB,	(0xff << 8)	/* AC Bias pin f.equ	ency */
.equ	 LCCR3_ACB_S,	8
#endif

.equ	 LCCR3_API,	(0xf << 16)	/* AC Bias pin trasitions per interrupt */
.equ	 LCCR3_API_S,	16
.equ	 LCCR3_VSP,	(1 << 20)	/* vertical sync polarity */
.equ	 LCCR3_HSP,	(1 << 21)	/* horizontal sync polarity */
.equ	 LCCR3_PCP,	(1 << 22)	/* pixel clock polarity */
.equ	 LCCR3_OEP,	(1 << 23)	/* output enable polarity */
#if 0
.equ	 LCCR3_BPP,	(7 << 24)	/* bits per pixel */
.equ	 LCCR3_BPP_S,	24
#endif
.equ	 LCCR3_DPC,	(1 << 27)	/* double pixel clock mode */

.equ	 LCCR3_PDFOR_0,	 (0 << 30)
.equ	 LCCR3_PDFOR_1,	 (1 << 30)
.equ	 LCCR3_PDFOR_2,	 (2 << 30)
.equ	 LCCR3_PDFOR_3,	 (3 << 30)



.equ	 LCCR3_HorSnchH,	(LCCR3_HSP*0)	/*  Horizontal Synchronization	   */
					/*  pulse active High		   */
.equ	 LCCR3_HorSnchL,	(LCCR3_HSP*1)	/*  Horizontal Synchronization	   */

.equ	 LCCR3_VrtSnchH,	(LCCR3_VSP*0)	/*  Vertical Synchronization pulse */
					/*  active High			   */
.equ	 LCCR3_VrtSnchL,	(LCCR3_VSP*1)	/*  Vertical Synchronization pulse */
					/*  active Low			   */

.equ	 LCSR0_LDD,	(1 << 0)	/* LCD Disable Done */
.equ	 LCSR0_SOF,	(1 << 1)	/* Start of frame */
.equ	 LCSR0_BER,	(1 << 2)	/* Bus error */
.equ	 LCSR0_ABC,	(1 << 3)	/* AC Bias count */
.equ	 LCSR0_IUL,	(1 << 4)	/* input FIFO underrun Lower panel */
.equ	 LCSR0_IUU,	(1 << 5)	/* input FIFO underrun Upper panel */
.equ	 LCSR0_OU,	(1 << 6)	/* output FIFO underrun */
.equ	 LCSR0_QD,	(1 << 7)	/* quick disable */
.equ	 LCSR0_EOF0,	(1 << 8)	/* end of frame */
.equ	 LCSR0_BS,	(1 << 9)	/* branch status */
.equ	 LCSR0_SINT,	(1 << 10)	/* sub.equ	ent interrupt */

.equ	 LCSR1_SOF1,	(1 << 0)
.equ	 LCSR1_SOF2,	(1 << 1)
.equ	 LCSR1_SOF3,	(1 << 2)
.equ	 LCSR1_SOF4,	(1 << 3)
.equ	 LCSR1_SOF5,	(1 << 4)
.equ	 LCSR1_SOF6,	(1 << 5)

.equ	 LCSR1_EOF1,	(1 << 8)
.equ	 LCSR1_EOF2,	(1 << 9)
.equ	 LCSR1_EOF3,	(1 << 10)
.equ	 LCSR1_EOF4,	(1 << 11)
.equ	 LCSR1_EOF5,	(1 << 12)
.equ	 LCSR1_EOF6,	(1 << 13)

.equ	 LCSR1_BS1,	(1 << 16)
.equ	 LCSR1_BS2,	(1 << 17)
.equ	 LCSR1_BS3,	(1 << 18)
.equ	 LCSR1_BS4,	(1 << 19)
.equ	 LCSR1_BS5,	(1 << 20)
.equ	 LCSR1_BS6,	(1 << 21)

.equ	 LCSR1_IU2,	(1 << 25)
.equ	 LCSR1_IU3,	(1 << 26)
.equ	 LCSR1_IU4,	(1 << 27)
.equ	 LCSR1_IU5,	(1 << 28)
.equ	 LCSR1_IU6,	(1 << 29)

.equ	 LDCMD_PAL,	(1 << 26)	/* instructs DMA to load palette buffer */
.equ	 LDCMD_SOFINT,	(1 << 22)
.equ	 LDCMD_EOFINT,	(1 << 21)

/*
 * Memory controller
 */
.equ	 MEMC_BASE,	(0x48000000)  /* Base of Memory Controller */
.equ	 MDCNFG_OFFSET,	0x0
.equ	 MDREFR_OFFSET,	0x4
.equ	 MSC0_OFFSET,	0x8
.equ	 MSC1_OFFSET,	0xC
.equ	 MSC2_OFFSET,	0x10
.equ	 MECR_OFFSET,	0x14
.equ	 SXLCR_OFFSET,	0x18
.equ	 SXCNFG_OFFSET,	0x1C
.equ	 FLYCNFG_OFFSET,	0x20
.equ	 SXMRS_OFFSET,	0x24
.equ	 MCMEM0_OFFSET,	0x28
.equ	 MCMEM1_OFFSET,	0x2C
.equ	 MCATT0_OFFSET,	0x30
.equ	 MCATT1_OFFSET,	0x34
.equ	 MCIO0_OFFSET,	0x38
.equ	 MCIO1_OFFSET,	0x3C
.equ	 MDMRS_OFFSET,	0x40

.equ	 MDCNFG,	(0x48000000)  /* SDRAM Configuration Register 0 */
.equ	 MDCNFG_DE0,	0x00000001
.equ	 MDCNFG_DE1,	0x00000002
.equ	 MDCNFG_DE2,	0x00010000
.equ	 MDCNFG_DE3,	0x00020000
.equ	 MDCNFG_DWID0,	0x00000004

.equ	 MDREFR,	(0x48000004)  /* SDRAM Refresh Control Register */
.equ	 MSC0,		(0x48000008)  /* Static Memory Control Register 0 */
.equ	 MSC1,		(0x4800000C)  /* Static Memory Control Register 1 */
.equ	 MSC2,		(0x48000010)  /* Static Memory Control Register 2 */
.equ	 MECR,		(0x48000014)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
.equ	 SXLCR,		(0x48000018)  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
.equ	 SXCNFG,	(0x4800001C)  /* Synchronous Static Memory Control Register */
.equ	 SXMRS,		(0x48000024)  /* MRS value to be written to Synchronous Flash or SMROM */
.equ	 MCMEM0,	(0x48000028)  /* Card interface Common Memory Space Socket 0 Timing */
.equ	 MCMEM1,	(0x4800002C)  /* Card interface Common Memory Space Socket 1 Timing */
.equ	 MCATT0,	(0x48000030)  /* Card interface Attribute Space Socket 0 Timing Configuration */
.equ	 MCATT1,	(0x48000034)  /* Card interface Attribute Space Socket 1 Timing Configuration */
.equ	 MCIO0,		(0x48000038)  /* Card interface I/O Space Socket 0 Timing Configuration */
.equ	 MCIO1,		(0x4800003C)  /* Card interface I/O Space Socket 1 Timing Configuration */
.equ	 MDMRS,		(0x48000040)  /* MRS value to be written to SDRAM */
.equ	 BOOT_DEF,	(0x48000044)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */

.equ	 MDREFR_K2FREE,	(1 << 25)	/* SDRAM Free-Running Control */
.equ	 MDREFR_K1FREE,	(1 << 24)	/* SDRAM Free-Running Control */
.equ	 MDREFR_K0FREE,	(1 << 23)	/* SDRAM Free-Running Control */
.equ	 MDREFR_SLFRSH,	(1 << 22)	/* SDRAM Self-Refresh Control/Status */
.equ