pxa-regs.inc

一个可以驱动 onenand的代码,使用ADS编译

.equ	 ICFP2,		(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
.equ	 ICPR2,		(0x40D000AC)  /* Interrupt Controller Pending Register 2 */


/* GPIO alternate function assignments */
.equ	 GPIO1_RST,		1	/* reset */
.equ	 GPIO6_MMCCLK,		6	/* MMC Clock */
.equ	 GPIO8_48MHz,		7	/* 48 MHz clock output */
.equ	 GPIO8_MMCCS0,		8	/* MMC Chip Select 0 */
.equ	 GPIO9_MMCCS1,		9	/* MMC Chip Select 1 */
.equ	 GPIO10_RTCCLK,		10	/* real time clock (1 Hz) */
.equ	 GPIO11_3_6MHz,		11	/* 3.6 MHz oscillator out */
.equ	 GPIO12_32KHz,		12	/* 32 kHz out */
.equ	 GPIO13_MBGNT,		13	/* memory controller grant */
.equ	 GPIO14_MBREQ,		14	/* alternate bus master .equ	est */
.equ	 GPIO15_nCS_1,		15	/* chip select 1 */
.equ	 GPIO16_PWM0,		16	/* PWM0 output */
.equ	 GPIO17_PWM1,		17	/* PWM1 output */
.equ	 GPIO18_RDY,		18	/* Ext. Bus Ready */
.equ	 GPIO19_DREQ1,		19	/* External DMA .equ	est */
.equ	 GPIO20_DREQ0,		20	/* External DMA .equ	est */
.equ	 GPIO23_SCLK,		23	/* SSP clock */
.equ	 GPIO24_SFRM,		24	/* SSP Frame */
.equ	 GPIO25_STXD,		25	/* SSP transmit */
.equ	 GPIO26_SRXD,		26	/* SSP receive */
.equ	 GPIO27_SEXTCLK,		27	/* SSP ext_clk */
.equ	 GPIO28_BITCLK,		28	/* AC97/I2S bit_clk */
.equ	 GPIO29_SDATA_IN,		29	/* AC97 Sdata_in0 / I2S Sdata_in */
.equ	 GPIO30_SDATA_OUT,	30	/* AC97/I2S Sdata_out */
.equ	 GPIO31_SYNC,		31	/* AC97/I2S sync */
.equ	 GPIO32_SDATA_IN1,	32	/* AC97 Sdata_in1 */
.equ	 GPIO33_nCS_5,		33	/* chip select 5 */
.equ	 GPIO34_FFRXD,		34	/* FFUART receive */
.equ	 GPIO34_MMCCS0,		34	/* MMC Chip Select 0 */
.equ	 GPIO35_FFCTS,		35	/* FFUART Clear to send */
.equ	 GPIO36_FFDCD,		36	/* FFUART Data carrier detect */
.equ	 GPIO37_FFDSR,		37	/* FFUART data set ready */
.equ	 GPIO38_FFRI,		38	/* FFUART Ring Indicator */
.equ	 GPIO39_MMCCS1,		39	/* MMC Chip Select 1 */
.equ	 GPIO39_FFTXD,		39	/* FFUART transmit data */
.equ	 GPIO40_FFDTR,		40	/* FFUART data terminal Ready */
.equ	 GPIO41_FFRTS,		41	/* FFUART .equ	est to send */
.equ	 GPIO42_BTRXD,		42	/* BTUART receive data */
.equ	 GPIO43_BTTXD,		43	/* BTUART transmit data */
.equ	 GPIO44_BTCTS,		44	/* BTUART clear to send */
.equ	 GPIO45_BTRTS,		45	/* BTUART .equ	est to send */
.equ	 GPIO46_ICPRXD,		46	/* ICP receive data */
.equ	 GPIO46_STRXD,		46	/* STD_UART receive data */
.equ	 GPIO47_ICPTXD,		47	/* ICP transmit data */
.equ	 GPIO47_STTXD,		47	/* STD_UART transmit data */
.equ	 GPIO48_nPOE,		48	/* Output Enable for Card Space */
.equ	 GPIO49_nPWE,		49	/* Write Enable for Card Space */
.equ	 GPIO50_nPIOR,		50	/* I/O Read for Card Space */
.equ	 GPIO51_nPIOW,		51	/* I/O Write for Card Space */
.equ	 GPIO52_nPCE_1,		52	/* Card Enable for Card Space */
.equ	 GPIO53_nPCE_2,		53	/* Card Enable for Card Space */
.equ	 GPIO53_MMCCLK,		53	/* MMC Clock */
.equ	 GPIO54_MMCCLK,		54	/* MMC Clock */
.equ	 GPIO54_pSKTSEL,	54	/* Socket Select for Card Space */
.equ	 GPIO55_nPREG,		55	/* Card Address bit 26 */
.equ	 GPIO56_nPWAIT,		56	/* Wait signal for Card Space */
.equ	 GPIO57_nIOIS16,	57	/* Bus Width select for I/O Card Space */
.equ	 GPIO58_LDD_0,		58	/* LCD data pin 0 */
.equ	 GPIO59_LDD_1,		59	/* LCD data pin 1 */
.equ	 GPIO60_LDD_2,		60	/* LCD data pin 2 */
.equ	 GPIO61_LDD_3,		61	/* LCD data pin 3 */
.equ	 GPIO62_LDD_4,		62	/* LCD data pin 4 */
.equ	 GPIO63_LDD_5,		63	/* LCD data pin 5 */
.equ	 GPIO64_LDD_6,		64	/* LCD data pin 6 */
.equ	 GPIO65_LDD_7,		65	/* LCD data pin 7 */
.equ	 GPIO66_LDD_8,		66	/* LCD data pin 8 */
.equ	 GPIO66_MBREQ,		66	/* alternate bus master req */
.equ	 GPIO67_LDD_9,		67	/* LCD data pin 9 */
.equ	 GPIO67_MMCCS0,		67	/* MMC Chip Select 0 */
.equ	 GPIO68_LDD_10,		68	/* LCD data pin 10 */
.equ	 GPIO68_MMCCS1,		68	/* MMC Chip Select 1 */
.equ	 GPIO69_LDD_11,		69	/* LCD data pin 11 */
.equ	 GPIO69_MMCCLK,		69	/* MMC_CLK */
.equ	 GPIO70_LDD_12,		70	/* LCD data pin 12 */
.equ	 GPIO70_RTCCLK,		70	/* Real Time clock (1 Hz) */
.equ	 GPIO71_LDD_13,		71	/* LCD data pin 13 */
.equ	 GPIO71_3_6MHz,		71	/* 3.6 MHz Oscillator clock */
.equ	 GPIO72_LDD_14,		72	/* LCD data pin 14 */
.equ	 GPIO72_32kHz,		72	/* 32 kHz clock */
.equ	 GPIO73_LDD_15,		73	/* LCD data pin 15 */
.equ	 GPIO73_MBGNT,		73	/* Memory controller grant */
.equ	 GPIO74_LCD_FCLK,	74	/* LCD Frame clock */
.equ	 GPIO75_LCD_LCLK,	75	/* LCD line clock */
.equ	 GPIO76_LCD_PCLK,	76	/* LCD Pixel clock */
.equ	 GPIO77_LCD_ACBIAS,	77	/* LCD AC Bias */
.equ	 GPIO78_nCS_2,		78	/* chip select 2 */
.equ	 GPIO79_nCS_3,		79	/* chip select 3 */
.equ	 GPIO80_nCS_4,		80	/* chip select 4 */

/* GPIO alternate function mode & direction */

.equ	 GPIO_IN,		0x000
.equ	 GPIO_OUT,		0x080
.equ	 GPIO_ALT_FN_1_IN,	0x100
.equ	 GPIO_ALT_FN_1_OUT,	0x180
.equ	 GPIO_ALT_FN_2_IN,	0x200
.equ	 GPIO_ALT_FN_2_OUT,	0x280
.equ	 GPIO_ALT_FN_3_IN,	0x300
.equ	 GPIO_ALT_FN_3_OUT,	0x380
.equ	 GPIO_MD_MASK_NR,	0x07f
.equ	 GPIO_MD_MASK_DIR,	0x080
.equ	 GPIO_MD_MASK_FN,	0x300

.equ	 GPIO1_RTS_MD,		( 1 | GPIO_ALT_FN_1_IN)
.equ	 GPIO6_MMCCLK_MD,	( 6 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO8_48MHz_MD,	( 8 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO8_MMCCS0_MD,		( 8 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO9_MMCCS1_MD,		( 9 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO10_RTCCLK_MD,		(10 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO11_3_6MHz_MD,		(11 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO12_32KHz_MD,		(12 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO13_MBGNT_MD,		(13 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO14_MBREQ_MD,		(14 | GPIO_ALT_FN_1_IN)
.equ	 GPIO15_nCS_1_MD,		(15 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO16_PWM0_MD,		(16 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO17_PWM1_MD,		(17 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO18_RDY_MD,			(18 | GPIO_ALT_FN_1_IN)
.equ	 GPIO19_DREQ1_MD,		(19 | GPIO_ALT_FN_1_IN)
.equ	 GPIO20_DREQ0_MD,		(20 | GPIO_ALT_FN_1_IN)
.equ	 GPIO23_SCLK_md,		(23 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO24_SFRM_MD,		(24 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO25_STXD_MD,		(25 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO26_SRXD_MD,		(26 | GPIO_ALT_FN_1_IN)
.equ	 GPIO27_SEXTCLK_MD,		(27 | GPIO_ALT_FN_1_IN)
.equ	 GPIO28_BITCLK_AC97_MD,		(28 | GPIO_ALT_FN_1_IN)
.equ	 GPIO28_BITCLK_I2S_MD,		(28 | GPIO_ALT_FN_2_IN)
.equ	 GPIO29_SDATA_IN_AC97_MD, 	(29 | GPIO_ALT_FN_1_IN)
.equ	 GPIO29_SDATA_IN_I2S_MD,	(29 | GPIO_ALT_FN_2_IN)
.equ	 GPIO30_SDATA_OUT_AC97_MD,	(30 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO30_SDATA_OUT_I2S_MD, 	(30 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO31_SYNC_AC97_MD,		(31 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO31_SYNC_I2S_MD,		(31 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO32_SDATA_IN1_AC97_MD,	(32 | GPIO_ALT_FN_1_IN)
.equ	 GPIO33_nCS_5_MD,		(33 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO34_FFRXD_MD,		(34 | GPIO_ALT_FN_1_IN)
.equ	 GPIO34_MMCCS0_MD,		(34 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO35_FFCTS_MD,		(35 | GPIO_ALT_FN_1_IN)
.equ	 GPIO36_FFDCD_MD,		(36 | GPIO_ALT_FN_1_IN)
.equ	 GPIO37_FFDSR_MD,		(37 | GPIO_ALT_FN_1_IN)
.equ	 GPIO38_FFRI_MD,		(38 | GPIO_ALT_FN_1_IN)
.equ	 GPIO39_MMCCS1_MD,		(39 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO39_FFTXD_MD,		(39 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO40_FFDTR_MD,		(40 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO41_FFRTS_MD,		(41 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO42_BTRXD_MD,		(42 | GPIO_ALT_FN_1_IN)
.equ	 GPIO43_BTTXD_MD,		(43 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO44_BTCTS_MD,		(44 | GPIO_ALT_FN_1_IN)
.equ	 GPIO45_BTRTS_MD,		(45 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO46_ICPRXD_MD,		(46 | GPIO_ALT_FN_1_IN)
.equ	 GPIO46_STRXD_MD,		(46 | GPIO_ALT_FN_2_IN)
.equ	 GPIO47_ICPTXD_MD,		(47 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO47_STTXD_MD,		(47 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO48_nPOE_MD,		(48 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO49_nPWE_MD,		(49 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO50_nPIOR_MD,		(50 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO51_nPIOW_MD,		(51 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO52_nPCE_1_MD,		(52 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO53_nPCE_2_MD,		(53 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO53_MMCCLK_MD,		(53 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO54_MMCCLK_MD,		(54 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO54_pSKTSEL_MD,		(54 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO55_nPREG_MD,		(55 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO56_nPWAIT_MD,		(56 | GPIO_ALT_FN_1_IN)
.equ	 GPIO57_nIOIS16_MD,		(57 | GPIO_ALT_FN_1_IN)
.equ	 GPIO58_LDD_0_MD,		(58 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO59_LDD_1_MD,		(59 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO60_LDD_2_MD,		(60 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO61_LDD_3_MD,		(61 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO62_LDD_4_MD,		(62 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO63_LDD_5_MD,		(63 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO64_LDD_6_MD,		(64 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO65_LDD_7_MD,		(65 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO66_LDD_8_MD,		(66 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO66_MBREQ_MD,		(66 | GPIO_ALT_FN_1_IN)
.equ	 GPIO67_LDD_9_MD,		(67 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO67_MMCCS0_MD,		(67 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO68_LDD_10_MD,		(68 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO68_MMCCS1_MD,		(68 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO69_LDD_11_MD,		(69 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO69_MMCCLK_MD,		(69 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO70_LDD_12_MD,		(70 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO70_RTCCLK_MD,		(70 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO71_LDD_13_MD,		(71 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO71_3_6MHz_MD,		(71 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO72_LDD_14_MD,		(72 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO72_32kHz_MD,		(72 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO73_LDD_15_MD,		(73 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO73_MBGNT_MD,		(73 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO74_LCD_FCLK_MD,		(74 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO75_LCD_LCLK_MD,		(75 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO76_LCD_PCLK_MD,		(76 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO77_LCD_ACBIAS_MD,		(77 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO78_nCS_2_MD,		(78 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO79_nCS_3_MD,		(79 | GPIO_ALT_FN_2_OUT)
.equ	 GPIO80_nCS_4_MD,		(80 | GPIO_ALT_FN_2_OUT)

.equ	 GPIO117_SCL,	     		(117 | GPIO_ALT_FN_1_OUT)
.equ	 GPIO118_SDA,	     		(118 | GPIO_ALT_FN_1_OUT)

/*
 * Power Manager
 */
.equ	 PMCR,		(0x40F00000)  /* Power Manager Control Register */
.equ	 PSSR,		(0x40F00004)  /* Power Manager Sleep Status Register */
.equ	 PSPR,		(0x40F00008)  /* Power Manager Scratch Pad Register */
.equ	 PWER,		(0x40F0000C)  /* Power Manager Wake-up Enable Register */
.equ	 PRER,		(0x40F00010)  /* Power Manager GPIO Rising-Edge Detect Enable Register */
.equ	 PFER,		(0x40F00014)  /* Power Manager GPIO Falling-Edge Detect Enable Register */
.equ	 PEDR,		(0x40F00018)  /* Power Manager GPIO Edge Detect Status Register */
.equ	 PCFR,		(0x40F0001C)  /* Power Manager General Configuration Register */
.equ	 PGSR0,		(0x40F00020)  /* Power Manager GPIO Sleep State Register for GP[31-0] */
.equ	 PGSR1,		(0x40F00024)  /* Power Manager GPIO Sleep State Register for GP[63-32] */
.equ	 PGSR2,		(0x40F00028)  /* Power Manager GPIO Sleep State Register for GP[84-64] */
.equ	 PGSR3,		(0x40F0002C)  /* Power Manager GPIO Sleep State Register for GP[118-96] */
.equ	 RCSR,		(0x40F00030)  /* Reset Controller Status Register */

.equ		   PSLR,	   (0x40F00034)	/* Power Manager Sleep Config Register */
.equ		   PSTR,	   (0x40F00038)	/* Power Manager Standby Config Register */
.equ		   PSNR,	   (0x40F0003C)	/* Power Manager Sense Config Register */
.equ		   PVCR,	   (0x40F00040)	/* Power Manager VoltageControl Register */
.equ		   PKWR,	   (0x40F00050)	/* Power Manager KB Wake-up Enable Reg */
.equ		   PKSR,	   (0x40F00054)	/* Power Manager KB Level-Detect Register */
@;.equ		   PCMD(x), (0x40F00080 + x*4)
.equ		   PCMD0,   (0x40F00080 + 0 * 4)
.equ		   PCMD1,   (0x40F00080 + 1 * 4)
.equ		   PCMD2,   (0x40F00080 + 2 * 4)
.equ		   PCMD3,   (0x40F00080 + 3 * 4)
.equ		   PCMD4,   (0x40F00080 + 4 * 4)
.equ		   PCMD5,   (0x40F00080 + 5 * 4)
.equ		   PCMD6,   (0x40F00080 + 6 * 4)
.equ		   PCMD7,   (0x40F00080 + 7 * 4)
.equ		   PCMD8,   (0x40F00080 + 8 * 4)
.equ		   PCMD9,   (0x40F00080 + 9 * 4)
.equ		   PCMD10,  (0x40F00080 + 10 * 4)
.equ		   PCMD11,  (0x40F00080 + 11 * 4)
.equ		   PCMD12,  (0x40F00080 + 12 * 4)
.equ		   PCMD13,  (0x40F00080 + 13 * 4)
.equ		   PCMD14,  (0x40F00080 + 14 * 4)
.equ		   PCMD15,  (0x40F00080 + 15 * 4)
.equ		   PCMD16,  (0x40F00080 + 16 * 4)
.equ		   PCMD17,  (0x40F00080 + 17 * 4)
.equ		   PCMD18,  (0x40F00080 + 18 * 4)
.equ		   PCMD19,  (0x40F00080 + 19 * 4)
.equ		   PCMD20,  (0x40F00080 + 20 * 4)
.equ		   PCMD21,  (0x40F00080 + 21 * 4)
.equ		   PCMD22,  (0x40F00080 + 22 * 4)
.equ		   PCMD23,  (0x40F00080 + 23 * 4)
.equ		   PCMD24,  (0x40F00080 + 24 * 4)
.equ		   PCMD25,  (0x40F00080 + 25 * 4)
.equ		   PCMD26,  (0x40F00080 + 26 * 4)
.equ		   PCMD27,  (0x40F00080 + 27 * 4)
.equ		   PCMD28,  (0x40F00080 + 28 * 4)
.equ		   PCMD29,  (0x40F00080 + 29 * 4)
.equ		   PCMD30,  (0x40F00080 + 30 * 4)
.equ		   PCMD31,  (0x40F00080 + 31 * 4)

.equ		   PCMD_MBC,    (1<<12)
.equ		   PCMD_DCE,    (1<<11)
.equ		   PCMD_LC,     (1<<10)
/* FIXME:  PCMD_SQC need be checked.   */
.equ		   PCMD_SQC,    (3<<8)  /* currently only bit 8 is changerable, */
				/* bit 9 should be 0 all day. */
.equ	 PVCR_VCSA,		   (0x1<<14)
.equ	 PVCR_CommandDelay,	   (0xf80)
/* define MACRO for Power Manager General Configuration Register (PCFR) */
.equ	 PCFR_FVC,		   (0x1 << 10)
.equ	 PCFR_PI2C_EN,		   (0x1 << 6)

.equ	 PSSR_OTGPH,	(1 << 6)	/* OTG Peripheral control Hold */
.equ	 PSSR_RDH,	(1 << 5)	/* Read Disable Hold */
.equ	 PSSR_PH,	(1 << 4)	/* Peripheral Control Hold */
.equ	 PSSR_VFS,	(1 << 2)	/* VDD Fault Status */
.equ	 PSSR_BFS,	(1 << 1)	/* Battery Fault Status */
.equ	 PSSR_SSS,	(1 << 0)	/* Software Sleep Status */