pxa-regs.inc

一个可以驱动 onenand的代码,使用ADS编译

.equ	 UDCCS13,		(0x40600044)  /* UDC Endpoint 13 (IN) Control/Status Register */

.equ	 UDCCS_II_TFS,	(1 << 0)	/* Transmit FIFO service */
.equ	 UDCCS_II_TPC,	(1 << 1)	/* Transmit packet complete */
.equ	 UDCCS_II_FTF,	(1 << 2)	/* Flush Tx FIFO */
.equ	 UDCCS_II_TUR,	(1 << 3)	/* Transmit FIFO underrun */
.equ	 UDCCS_II_TSP,	(1 << 7)	/* Transmit short packet */

/* Isochronous OUT - Endpoint 4,9,14 */
.equ	 UDCCS4,		(0x40600020)  /* UDC Endpoint 4 (OUT) Control/Status Register */
.equ	 UDCCS9,		(0x40600034)  /* UDC Endpoint 9 (OUT) Control/Status Register */
.equ	 UDCCS14,		(0x40600048)  /* UDC Endpoint 14 (OUT) Control/Status Register */

.equ	 UDCCS_IO_RFS,	(1 << 0)	/* Receive FIFO service */
.equ	 UDCCS_IO_RPC,	(1 << 1)	/* Receive packet complete */
.equ	 UDCCS_IO_ROF,	(1 << 3)	/* Receive overflow */
.equ	 UDCCS_IO_DME,	(1 << 3)	/* DMA enable */
.equ	 UDCCS_IO_RNE,	(1 << 6)	/* Receive FIFO not empty */
.equ	 UDCCS_IO_RSP,	(1 << 7)	/* Receive short packet */

/* Interrupt IN - Endpoint 5,10,15 */
.equ	 UDCCS5,		(0x40600024)  /* UDC Endpoint 5 (Interrupt) Control/Status Register */
.equ	 UDCCS10,		(0x40600038)  /* UDC Endpoint 10 (Interrupt) Control/Status Register */
.equ	 UDCCS15,		(0x4060004C)  /* UDC Endpoint 15 (Interrupt) Control/Status Register */

.equ	 UDCCS_INT_TFS,	(1 << 0)	/* Transmit FIFO service */
.equ	 UDCCS_INT_TPC,	(1 << 1)	/* Transmit packet complete */
.equ	 UDCCS_INT_FTF,	(1 << 2)	/* Flush Tx FIFO */
.equ	 UDCCS_INT_TUR,	(1 << 3)	/* Transmit FIFO underrun */
.equ	 UDCCS_INT_SST,	(1 << 4)	/* Sent stall */
.equ	 UDCCS_INT_FST,	(1 << 5)	/* Force stall */
.equ	 UDCCS_INT_TSP,	(1 << 7)	/* Transmit short packet */

.equ	 UFNRH,		(0x40600060)  /* UDC Frame Number Register High */
.equ	 UFNRL,		(0x40600064)  /* UDC Frame Number Register Low */
.equ	 UBCR2,		(0x40600068)  /* UDC Byte Count Reg 2 */
.equ	 UBCR4,		(0x4060006c)  /* UDC Byte Count Reg 4 */
.equ	 UBCR7,		(0x40600070)  /* UDC Byte Count Reg 7 */
.equ	 UBCR9,		(0x40600074)  /* UDC Byte Count Reg 9 */
.equ	 UBCR12,	(0x40600078)  /* UDC Byte Count Reg 12 */
.equ	 UBCR14,	(0x4060007c)  /* UDC Byte Count Reg 14 */
.equ	 UDDR0,		(0x40600080)  /* UDC Endpoint 0 Data Register */
.equ	 UDDR1,		(0x40600100)  /* UDC Endpoint 1 Data Register */
.equ	 UDDR2,		(0x40600180)  /* UDC Endpoint 2 Data Register */
.equ	 UDDR3,		(0x40600200)  /* UDC Endpoint 3 Data Register */
.equ	 UDDR4,		(0x40600400)  /* UDC Endpoint 4 Data Register */
.equ	 UDDR5,		(0x406000A0)  /* UDC Endpoint 5 Data Register */
.equ	 UDDR6,		(0x40600600)  /* UDC Endpoint 6 Data Register */
.equ	 UDDR7,		(0x40600680)  /* UDC Endpoint 7 Data Register */
.equ	 UDDR8,		(0x40600700)  /* UDC Endpoint 8 Data Register */
.equ	 UDDR9,		(0x40600900)  /* UDC Endpoint 9 Data Register */
.equ	 UDDR10,	(0x406000C0)  /* UDC Endpoint 10 Data Register */
.equ	 UDDR11,	(0x40600B00)  /* UDC Endpoint 11 Data Register */
.equ	 UDDR12,	(0x40600B80)  /* UDC Endpoint 12 Data Register */
.equ	 UDDR13,	(0x40600C00)  /* UDC Endpoint 13 Data Register */
.equ	 UDDR14,	(0x40600E00)  /* UDC Endpoint 14 Data Register */
.equ	 UDDR15,	(0x406000E0)  /* UDC Endpoint 15 Data Register */

.equ	 UICR0,		(0x40600050)  /* UDC Interrupt Control Register 0 */

.equ	 UICR0_IM0,	(1 << 0)	/* Interrupt mask ep 0 */
.equ	 UICR0_IM1,	(1 << 1)	/* Interrupt mask ep 1 */
.equ	 UICR0_IM2,	(1 << 2)	/* Interrupt mask ep 2 */
.equ	 UICR0_IM3,	(1 << 3)	/* Interrupt mask ep 3 */
.equ	 UICR0_IM4,	(1 << 4)	/* Interrupt mask ep 4 */
.equ	 UICR0_IM5,	(1 << 5)	/* Interrupt mask ep 5 */
.equ	 UICR0_IM6,	(1 << 6)	/* Interrupt mask ep 6 */
.equ	 UICR0_IM7,	(1 << 7)	/* Interrupt mask ep 7 */

.equ	 UICR1,		(0x40600054)  /* UDC Interrupt Control Register 1 */

.equ	 UICR1_IM8,	(1 << 0)	/* Interrupt mask ep 8 */
.equ	 UICR1_IM9,	(1 << 1)	/* Interrupt mask ep 9 */
.equ	 UICR1_IM10,	(1 << 2)	/* Interrupt mask ep 10 */
.equ	 UICR1_IM11,	(1 << 3)	/* Interrupt mask ep 11 */
.equ	 UICR1_IM12,	(1 << 4)	/* Interrupt mask ep 12 */
.equ	 UICR1_IM13,	(1 << 5)	/* Interrupt mask ep 13 */
.equ	 UICR1_IM14,	(1 << 6)	/* Interrupt mask ep 14 */
.equ	 UICR1_IM15,	(1 << 7)	/* Interrupt mask ep 15 */

.equ	 USIR0,		(0x40600058)  /* UDC Status Interrupt Register 0 */

.equ	 USIR0_IR0,	(1 << 0)	/* Interrup .equ	est ep 0 */
.equ	 USIR0_IR1,	(1 << 1)	/* Interrup .equ	est ep 1 */
.equ	 USIR0_IR2,	(1 << 2)	/* Interrup .equ	est ep 2 */
.equ	 USIR0_IR3,	(1 << 3)	/* Interrup .equ	est ep 3 */
.equ	 USIR0_IR4,	(1 << 4)	/* Interrup .equ	est ep 4 */
.equ	 USIR0_IR5,	(1 << 5)	/* Interrup .equ	est ep 5 */
.equ	 USIR0_IR6,	(1 << 6)	/* Interrup .equ	est ep 6 */
.equ	 USIR0_IR7,	(1 << 7)	/* Interrup .equ	est ep 7 */

.equ	 USIR1,		(0x4060005C)  /* UDC Status Interrupt Register 1 */

.equ	 USIR1_IR8,	(1 << 0)	/* Interrup .equ	est ep 8 */
.equ	 USIR1_IR9,	(1 << 1)	/* Interrup .equ	est ep 9 */
.equ	 USIR1_IR10,	(1 << 2)	/* Interrup .equ	est ep 10 */
.equ	 USIR1_IR11,	(1 << 3)	/* Interrup .equ	est ep 11 */
.equ	 USIR1_IR12,	(1 << 4)	/* Interrup .equ	est ep 12 */
.equ	 USIR1_IR13,	(1 << 5)	/* Interrup .equ	est ep 13 */
.equ	 USIR1_IR14,	(1 << 6)	/* Interrup .equ	est ep 14 */
.equ	 USIR1_IR15,	(1 << 7)	/* Interrup .equ	est ep 15 */

/*
 * USB Host Controller
 */
.equ	 UHCREV,	(0x4C000000)
.equ	 UHCHCON,	(0x4C000004)
.equ	 UHCCOMS,	(0x4C000008)
.equ	 UHCINTS,	(0x4C00000C)
.equ	 UHCINTE,	(0x4C000010)
.equ	 UHCINTD,	(0x4C000014)
.equ	 UHCHCCA,	(0x4C000018)
.equ	 UHCPCED,	(0x4C00001C)
.equ	 UHCCHED,	(0x4C000020)
.equ	 UHCCCED,	(0x4C000024)
.equ	 UHCBHED,	(0x4C000028)
.equ	 UHCBCED,	(0x4C00002C)
.equ	 UHCDHEAD,	(0x4C000030)
.equ	 UHCFMI,	(0x4C000034)
.equ	 UHCFMR,	(0x4C000038)
.equ	 UHCFMN,	(0x4C00003C)
.equ	 UHCPERS,	(0x4C000040)
.equ	 UHCLST,	(0x4C000044)
.equ	 UHCRHDA,	(0x4C000048)
.equ	 UHCRHDB,	(0x4C00004C)
.equ	 UHCRHS,	(0x4C000050)
.equ	 UHCRHPS1,	(0x4C000054)
.equ	 UHCRHPS2,	(0x4C000058)
.equ	 UHCRHPS3,	(0x4C00005C)
.equ	 UHCSTAT,	(0x4C000060)
.equ	 UHCHR,		(0x4C000064)
.equ	 UHCHIE,	(0x4C000068)
.equ	 UHCHIT,	(0x4C00006C)

.equ	 UHCHR_FSBIR,	(1<<0)
.equ	 UHCHR_FHR,	(1<<1)
.equ	 UHCHR_CGR,	(1<<2)
.equ	 UHCHR_SSDC,	(1<<3)
.equ	 UHCHR_UIT,	(1<<4)
.equ	 UHCHR_SSE,	(1<<5)
.equ	 UHCHR_PSPL,	(1<<6)
.equ	 UHCHR_PCPL,	(1<<7)
.equ	 UHCHR_SSEP0,	(1<<9)
.equ	 UHCHR_SSEP1,	(1<<10)
.equ	 UHCHR_SSEP2,	(1<<11)

.equ	 UHCHIE_UPRIE,	(1<<13)
.equ	 UHCHIE_UPS2IE,	(1<<12)
.equ	 UHCHIE_UPS1IE,	(1<<11)
.equ	 UHCHIE_TAIE,	(1<<10)
.equ	 UHCHIE_HBAIE,	(1<<8)
.equ	 UHCHIE_RWIE,	(1<<7)


/*
 * Fast Infrared Communication Port
 */
.equ	 ICCR0,		(0x40800000)  /* ICP Control Register 0 */
.equ	 ICCR1,		(0x40800004)  /* ICP Control Register 1 */
.equ	 ICCR2,		(0x40800008)  /* ICP Control Register 2 */
.equ	 ICDR,		(0x4080000c)  /* ICP Data Register */
.equ	 ICSR0,		(0x40800014)  /* ICP Status Register 0 */
.equ	 ICSR1,		(0x40800018)  /* ICP Status Register 1 */

/*
 * Real Time Clock
 */
.equ	 RCNR,		(0x40900000)  /* RTC Count Register */
.equ	 RTAR,		(0x40900004)  /* RTC Alarm Register */
.equ	 RTSR,		(0x40900008)  /* RTC Status Register */
.equ	 RTTR,		(0x4090000C)  /* RTC Timer Trim Register */
.equ	 RDAR1,	   (0x40900018)  /* Wristwatch Day Alarm Reg 1 */
.equ	 RDAR2,	   (0x40900020)  /* Wristwatch Day Alarm Reg 2 */
.equ	 RYAR1,	   (0x4090001C)  /* Wristwatch Year Alarm Reg 1 */
.equ	 RYAR2,	   (0x40900024)  /* Wristwatch Year Alarm Reg 2 */
.equ	 SWAR1,	   (0x4090002C)  /* Stopwatch Alarm Register 1 */
.equ	 SWAR2,	   (0x40900030)  /* Stopwatch Alarm Register 2 */
.equ	 PIAR,	   (0x40900038)  /* Periodic Interrupt Alarm Register */
.equ	 RDCR,	   (0x40900010)  /* RTC Day Count Register. */
.equ	 RYCR,	   (0x40900014)  /* RTC Year Count Register. */
.equ	 SWCR,	   (0x40900028)  /* Stopwatch Count Register */
.equ	 RTCPICR,	(0x40900034)  /* Periodic Interrupt Counter Register */

.equ	 RTSR_PICE,  	(1 << 15)   /* Peridoc interrupt count enable */
.equ	 RTSR_PIALE, 	(1 << 14)   /* Peridoc interrupt Alarm enable */
.equ	 RTSR_PIAL,  	(1 << 13)   /* Peridoc  interrupt Alarm status */
.equ	 RTSR_HZE,	(1 << 3)	/* HZ interrupt enable */
.equ	 RTSR_ALE,	(1 << 2)	/* RTC alarm interrupt enable */
.equ	 RTSR_HZ,	(1 << 1)	/* HZ rising-edge detected */
.equ	 RTSR_AL,	(1 << 0)	/* RTC alarm detected */

/*
 * OS Timer & Match Registers
 */
.equ	 OSMR0,		(0x40A00000)  /* */
.equ	 OSMR1,		(0x40A00004)  /* */
.equ	 OSMR2,		(0x40A00008)  /* */
.equ	 OSMR3,		(0x40A0000C)  /* */
.equ	 OSCR,		(0x40A00010)  /* OS Timer Counter Register */
.equ	 OSSR,		(0x40A00014)  /* OS Timer Status Register */
.equ	 OWER,		(0x40A00018)  /* OS Timer Watchdog Enable Register */
.equ	 OIER,		(0x40A0001C)  /* OS Timer Interrupt Enable Register */

.equ	 OSSR_M3,	(1 << 3)	/* Match status channel 3 */
.equ	 OSSR_M2,	(1 << 2)	/* Match status channel 2 */
.equ	 OSSR_M1,	(1 << 1)	/* Match status channel 1 */
.equ	 OSSR_M0,	(1 << 0)	/* Match status channel 0 */

.equ	 OWER_WME,	(1 << 0)	/* Watchdog Match Enable */

.equ	 OIER_E3,	(1 << 3)	/* Interrupt enable channel 3 */
.equ	 OIER_E2,	(1 << 2)	/* Interrupt enable channel 2 */
.equ	 OIER_E1,	(1 << 1)	/* Interrupt enable channel 1 */
.equ	 OIER_E0,	(1 << 0)	/* Interrupt enable channel 0 */

/*
 * Pulse Width Modulator
 */
.equ	 PWM_CTRL0,	(0x40B00000)  /* PWM 0 Control Register */
.equ	 PWM_PWDUTY0,	(0x40B00004)  /* PWM 0 Duty Cycle Register */
.equ	 PWM_PERVAL0,	(0x40B00008)  /* PWM 0 Period Control Register */

.equ	 PWM_CTRL1,	(0x40C00000)  /* PWM 1Control Register */
.equ	 PWM_PWDUTY1,	(0x40C00004)  /* PWM 1 Duty Cycle Register */
.equ	 PWM_PERVAL1,	(0x40C00008)  /* PWM 1 Period Control Register */

/*
 * Interrupt Controller
 */
.equ	 ICIP,		(0x40D00000)  /* Interrupt Controller IRQ Pending Register */
.equ	 ICMR,		(0x40D00004)  /* Interrupt Controller Mask Register */
.equ	 ICLR,		(0x40D00008)  /* Interrupt Controller Level Register */
.equ	 ICFP,		(0x40D0000C)  /* Interrupt Controller FIQ Pending Register */
.equ	 ICPR,		(0x40D00010)  /* Interrupt Controller Pending Register */
.equ	 ICCR,		(0x40D00014)  /* Interrupt Controller Control Register */

/*
 * General Purpose I/O
 */
.equ	 GPLR0,		(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
.equ	 GPLR1,		(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
.equ	 GPLR2,		(0x40E00008)  /* GPIO Pin-Level Register GPIO<80:64> */

.equ	 GPDR0,		(0x40E0000C)  /* GPIO Pin Direction Register GPIO<31:0> */
.equ	 GPDR1,		(0x40E00010)  /* GPIO Pin Direction Register GPIO<63:32> */
.equ	 GPDR2,		(0x40E00014)  /* GPIO Pin Direction Register GPIO<80:64> */

.equ	 GPSR0,		(0x40E00018)  /* GPIO Pin Output Set Register GPIO<31:0> */
.equ	 GPSR1,		(0x40E0001C)  /* GPIO Pin Output Set Register GPIO<63:32> */
.equ	 GPSR2,		(0x40E00020)  /* GPIO Pin Output Set Register GPIO<80:64> */

.equ	 GPCR0,		(0x40E00024)  /* GPIO Pin Output Clear Register GPIO<31:0> */
.equ	 GPCR1,		(0x40E00028)  /* GPIO Pin Output Clear Register GPIO <63:32> */
.equ	 GPCR2,		(0x40E0002C)  /* GPIO Pin Output Clear Register GPIO <80:64> */

.equ	 GRER0,		(0x40E00030)  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
.equ	 GRER1,		(0x40E00034)  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
.equ	 GRER2,		(0x40E00038)  /* GPIO Rising-Edge Detect Register GPIO<80:64> */

.equ	 GFER0,		(0x40E0003C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
.equ	 GFER1,		(0x40E00040)  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
.equ	 GFER2,		(0x40E00044)  /* GPIO Falling-Edge Detect Register GPIO<80:64> */

.equ	 GEDR0,		(0x40E00048)  /* GPIO Edge Detect Status Register GPIO<31:0> */
.equ	 GEDR1,		(0x40E0004C)  /* GPIO Edge Detect Status Register GPIO<63:32> */
.equ	 GEDR2,		(0x40E00050)  /* GPIO Edge Detect Status Register GPIO<80:64> */

.equ	 GAFR0_L,	(0x40E00054)  /* GPIO Alternate Function Select Register GPIO<15:0> */
.equ	 GAFR0_U,	(0x40E00058)  /* GPIO Alternate Function Select Register GPIO<31:16> */
.equ	 GAFR1_L,	(0x40E0005C)  /* GPIO Alternate Function Select Register GPIO<47:32> */
.equ	 GAFR1_U,	(0x40E00060)  /* GPIO Alternate Function Select Register GPIO<63:48> */
.equ	 GAFR2_L,	(0x40E00064)  /* GPIO Alternate Function Select Register GPIO<79:64> */
.equ	 GAFR2_U,	(0x40E00068)  /* GPIO Alternate Function Select Register GPIO 80 */


/* Interrupt Controller */

.equ	 ICIP2,		(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
.equ	 ICMR2,		(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
.equ	 ICLR2,		(0x40D000A4)  /* Interrupt Controller Level Register 2 */