pxa-regs.inc

一个可以驱动 onenand的代码,使用ADS编译

.equ	 BTMCR,		(0x40200010)  /* Modem Control Register (read/write) */
.equ	 BTLSR,		(0x40200014)  /* Line Status Register (read only) */
.equ	 BTMSR,		(0x40200018)  /* Modem Status Register (read only) */
.equ	 BTSPR,		(0x4020001C)  /* Scratch Pad Register (read/write) */
.equ	 BTISR,		(0x40200020)  /* Infrared Selection Register (read/write) */
.equ	 BTDLL,		(0x40200000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
.equ	 BTDLH,		(0x40200004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */

/* Standard UART (STUART) */
.equ	 STUART,	STRBR
.equ	 STRBR,		(0x40700000)  /* Receive Buffer Register (read only) */
.equ	 STTHR,		(0x40700000)  /* Transmit Holding Register (write only) */
.equ	 STIER,		(0x40700004)  /* Interrupt Enable Register (read/write) */
.equ	 STIIR,		(0x40700008)  /* Interrupt ID Register (read only) */
.equ	 STFCR,		(0x40700008)  /* FIFO Control Register (write only) */
.equ	 STLCR,		(0x4070000C)  /* Line Control Register (read/write) */
.equ	 STMCR,		(0x40700010)  /* Modem Control Register (read/write) */
.equ	 STLSR,		(0x40700014)  /* Line Status Register (read only) */
.equ	 STMSR,		(0x40700018)  /* Reserved */
.equ	 STSPR,		(0x4070001C)  /* Scratch Pad Register (read/write) */
.equ	 STISR,		(0x40700020)  /* Infrared Selection Register (read/write) */
.equ	 STDLL,		(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
.equ	 STDLH,		(0x40700004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */

.equ	 IER_DMAE,	(1 << 7)	/* DMA .equ	ests Enable */
.equ	 IER_UUE,	(1 << 6)	/* UART Unit Enable */
.equ	 IER_NRZE,	(1 << 5)	/* NRZ coding Enable */
.equ	 IER_RTIOE,	(1 << 4)	/* Receiver Time Out Interrupt Enable */
.equ	 IER_MIE,	(1 << 3)	/* Modem Interrupt Enable */
.equ	 IER_RLSE,	(1 << 2)	/* Receiver Line Status Interrupt Enable */
.equ	 IER_TIE,	(1 << 1)	/* Transmit Data .equ	est Interrupt Enable */
.equ	 IER_RAVIE,	(1 << 0)	/* Receiver Data Available Interrupt Enable */

.equ	 IIR_FIFOES1,	(1 << 7)	/* FIFO Mode Enable Status */
.equ	 IIR_FIFOES0,	(1 << 6)	/* FIFO Mode Enable Status */
.equ	 IIR_TOD,	(1 << 3)	/* Time Out Detected */
.equ	 IIR_IID2,	(1 << 2)	/* Interrupt Source Encoded */
.equ	 IIR_IID1,	(1 << 1)	/* Interrupt Source Encoded */
.equ	 IIR_IP,	(1 << 0)	/* Interrupt Pending (active low) */

.equ	 FCR_ITL2,	(1 << 7)	/* Interrupt Trigger Level */
.equ	 FCR_ITL1,	(1 << 6)	/* Interrupt Trigger Level */
.equ	 FCR_RESETTF,	(1 << 2)	/* Reset Transmitter FIFO */
.equ	 FCR_RESETRF,	(1 << 1)	/* Reset Receiver FIFO */
.equ	 FCR_TRFIFOE,	(1 << 0)	/* Transmit and Receive FIFO Enable */
.equ	 FCR_ITL_1,	(0)
.equ	 FCR_ITL_8,	(FCR_ITL1)
.equ	 FCR_ITL_16,	(FCR_ITL2)
.equ	 FCR_ITL_32,	(FCR_ITL2|FCR_ITL1)

.equ	 LCR_DLAB,	(1 << 7)	/* Divisor Latch Access Bit */
.equ	 LCR_SB,	(1 << 6)	/* Set Break */
.equ	 LCR_STKYP,	(1 << 5)	/* Sticky Parity */
.equ	 LCR_EPS,	(1 << 4)	/* Even Parity Select */
.equ	 LCR_PEN,	(1 << 3)	/* Parity Enable */
.equ	 LCR_STB,	(1 << 2)	/* Stop Bit */
.equ	 LCR_WLS1,	(1 << 1)	/* Word Length Select */
.equ	 LCR_WLS0,	(1 << 0)	/* Word Length Select */

.equ	 LSR_FIFOE,	(1 << 7)	/* FIFO Error Status */
.equ	 LSR_TEMT,	(1 << 6)	/* Transmitter Empty */
.equ	 LSR_TDRQ,	(1 << 5)	/* Transmit Data .equ	est */
.equ	 LSR_BI,	(1 << 4)	/* Break Interrupt */
.equ	 LSR_FE,	(1 << 3)	/* Framing Error */
.equ	 LSR_PE,	(1 << 2)	/* Parity Error */
.equ	 LSR_OE,	(1 << 1)	/* Overrun Error */
.equ	 LSR_DR,	(1 << 0)	/* Data Ready */

.equ	 MCR_LOOP,	(1 << 4)	
.equ	 MCR_OUT2,	(1 << 3)	/* force MSR_DCD in loopback mode */
.equ	 MCR_OUT1,	(1 << 2)	/* force MSR_RI in loopback mode */
.equ	 MCR_RTS,	(1 << 1)	/* .equ	est to Send */
.equ	 MCR_DTR,	(1 << 0)	/* Data Terminal Ready */

.equ	 MSR_DCD,	(1 << 7)	/* Data Carrier Detect */
.equ	 MSR_RIi,	(1 << 6)	/* Ring Indicator */
.equ	 MSR_DSR,	(1 << 5)	/* Data Set Ready */
.equ	 MSR_CTS,	(1 << 4)	/* Clear To Send */
.equ	 MSR_DDCD,	(1 << 3)	/* Delta Data Carrier Detect */
.equ	 MSR_TERI,	(1 << 2)	/* Trailing Edge Ring Indicator */
.equ	 MSR_DDSR,	(1 << 1)	/* Delta Data Set Ready */
.equ	 MSR_DCTS,	(1 << 0)	/* Delta Clear To Send */

/*
 * IrSR (Infrared Selection Register)
 */
.equ	 IrSR_OFFSET, 0x20

.equ	 IrSR_RXPL_NEG_IS_ZERO, (1<<4)
.equ	 IrSR_RXPL_POS_IS_ZERO, 0x0
.equ	 IrSR_TXPL_NEG_IS_ZERO, (1<<3)
.equ	 IrSR_TXPL_POS_IS_ZERO, 0x0
.equ	 IrSR_XMODE_PULSE_1_6,  (1<<2)
.equ	 IrSR_XMODE_PULSE_3_16, 0x0
.equ	 IrSR_RCVEIR_IR_MODE,   (1<<1)
.equ	 IrSR_RCVEIR_UART_MODE, 0x0
.equ	 IrSR_XMITIR_IR_MODE,   (1<<0)
.equ	 IrSR_XMITIR_UART_MODE, 0x0

/*
 * I2C registers
 */
.equ	 IBMR,		(0x40301680)  /* I2C Bus Monitor Register - IBMR */
.equ	 IDBR,		(0x40301688)  /* I2C Data Buffer Register - IDBR */
.equ	 ICR,		(0x40301690)  /* I2C Control Register - ICR */
.equ	 ISR,		(0x40301698)  /* I2C Status Register - ISR */
.equ	 ISAR,		(0x403016A0)  /* I2C Slave Address Register - ISAR */

.equ	 PWRIBMR,	(0x40f00180)  /* Power I2C Bus Monitor Register-IBMR */
.equ	 PWRIDBR,	(0x40f00188)  /* Power I2C Data Buffer Register-IDBR */
.equ	 PWRICR,	(0x40f00190)  /* Power I2C Control Register - ICR */
.equ	 PWRISR,	(0x40f00198)  /* Power I2C Status Register - ISR */
.equ	 PWRISAR,	(0x40f001A0)  /* Power I2C Slave Address Register-ISAR */

/* ----- Control register bits ---------------------------------------- */

.equ	 ICR_START,	0x1		/* start bit */
.equ	 ICR_STOP,	0x2		/* stop bit */
.equ	 ICR_ACKNAK,	0x4		/* send ACK(0) or NAK(1) */
.equ	 ICR_TB,	0x8		/* transfer byte bit */
.equ	 ICR_MA,	0x10		/* master abort */
.equ	 ICR_SCLE,	0x20		/* master clock enable */
.equ	 ICR_IUE,	0x40		/* unit enable */
.equ	 ICR_GCD,	0x80		/* general call disable */
.equ	 ICR_ITEIE,	0x100		/* enable tx interrupts */
.equ	 ICR_IRFIE,	0x200		/* enable rx interrupts */
.equ	 ICR_BEIE,	0x400		/* enable bus error ints */
.equ	 ICR_SSDIE,	0x800		/* slave STOP detected int enable */
.equ	 ICR_ALDIE,	0x1000		/* enable arbitration interrupt */
.equ	 ICR_SADIE,	0x2000		/* slave address detected int enable */
.equ	 ICR_UR,	0x4000		/* unit reset */
.equ	 ICR_FM,	0x8000		/* Fast Mode */

/* ----- Status register bits ----------------------------------------- */

.equ	 ISR_RWM,	0x1		/* read/write mode */
.equ	 ISR_ACKNAK,	0x2		/* ack/nak status */
.equ	 ISR_UB,	0x4		/* unit busy */
.equ	 ISR_IBB,	0x8		/* bus busy */
.equ	 ISR_SSD,	0x10		/* slave stop detected */
.equ	 ISR_ALD,	0x20		/* arbitration loss detected */
.equ	 ISR_ITE,	0x40		/* tx buffer empty */
.equ	 ISR_IRF,	0x80		/* rx buffer full */
.equ	 ISR_GCAD,	0x100		/* general call address detected */
.equ	 ISR_SAD,	0x200		/* slave address detected */
.equ	 ISR_BED,	0x400		/* bus error no ACK/NAK */


/*
 * AC97 Controller registers
 */
.equ	 POCR,		(0x40500000)  /* PCM Out Control Register */
.equ	 POCR_FEIE,	(1 << 3)	/* FIFO Error Interrupt Enable */

.equ	 PICR,		(0x40500004)  /* PCM In Control Register */
.equ	 PICR_FEIE,	(1 << 3)	/* FIFO Error Interrupt Enable */

.equ	 MCCR,		(0x40500008)  /* Mic In Control Register */
.equ	 MCCR_FEIE,	(1 << 3)	/* FIFO Error Interrupt Enable */

.equ	 GCR,		(0x4050000C)  /* Global Control Register */
.equ	 GCR_CDONE_IE,	(1 << 19)	/* Command Done Interrupt Enable */
.equ	 GCR_SDONE_IE,	(1 << 18)	/* Status Done Interrupt Enable */
.equ	 GCR_SECRDY_IEN,	(1 << 9)	/* Secondary Ready Interrupt Enable */
.equ	 GCR_PRIRDY_IEN,	(1 << 8)	/* Primary Ready Interrupt Enable */
.equ	 GCR_SECRES_IEN,	(1 << 5)	/* Secondary Resume Interrupt Enable */
.equ	 GCR_PRIRES_IEN,	(1 << 4)	/* Primary Resume Interrupt Enable */
.equ	 GCR_ACLINK_OFF,	(1 << 3)	/* AC-link Shut Off */
.equ	 GCR_WARM_RST,	(1 << 2)	/* AC97 Warm Reset */
.equ	 GCR_COLD_RST,	(1 << 1)	/* AC'97 Cold Reset (0 = active) */
.equ	 GCR_GIE,		(1 << 0)	/* Codec GPI Interrupt Enable */

.equ	 POSR,		(0x40500010)  /* PCM Out Status Register */
.equ	 POSR_FIFOE,	(1 << 4)	/* FIFO error */

.equ	 PISR,		(0x40500014)  /* PCM In Status Register */
.equ	 PISR_FIFOE,	(1 << 4)	/* FIFO error */

.equ	 MCSR,		(0x40500018)  /* Mic In Status Register */
.equ	 MCSR_FIFOE,	(1 << 4)	/* FIFO error */

.equ	 GSR,		(0x4050001C)  /* Global Status Register */
.equ	 GSR_CDONE,	(1 << 19)	/* Command Done */
.equ	 GSR_SDONE,	(1 << 18)	/* Status Done */
.equ	 GSR_RDCS,	(1 << 15)	/* Read Completion Status */
.equ	 GSR_BIT3SLT12,	(1 << 14)	/* Bit 3 of slot 12 */
.equ	 GSR_BIT2SLT12,	(1 << 13)	/* Bit 2 of slot 12 */
.equ	 GSR_BIT1SLT12,	(1 << 12)	/* Bit 1 of slot 12 */
.equ	 GSR_SECRES,	(1 << 11)	/* Secondary Resume Interrupt */
.equ	 GSR_PRIRES,	(1 << 10)	/* Primary Resume Interrupt */
.equ	 GSR_SCR,		(1 << 9)	/* Secondary Codec Ready */
.equ	 GSR_PCR,		(1 << 8)	/*  Primary Codec Ready */
.equ	 GSR_MINT,	(1 << 7)	/* Mic In Interrupt */
.equ	 GSR_POINT,	(1 << 6)	/* PCM Out Interrupt */
.equ	 GSR_PIINT,	(1 << 5)	/* PCM In Interrupt */
.equ	 GSR_MOINT,	(1 << 2)	/* Modem Out Interrupt */
.equ	 GSR_MIINT,	(1 << 1)	/* Modem In Interrupt */
.equ	 GSR_GSCI,	(1 << 0)	/* Codec GPI Status Change Interrupt */

.equ	 CAR,		(0x40500020)  /* CODEC Access Register */
.equ	 CAR_CAIP,	(1 << 0)	/* Codec Access In Progress */

.equ	 PCDR,		(0x40500040)  /* PCM FIFO Data Register */
.equ	 MCDR,		(0x40500060)  /* Mic-in FIFO Data Register */

.equ	 MOCR,		(0x40500100)  /* Modem Out Control Register */
.equ	 MOCR_FEIE,	(1 << 3)	/* FIFO Error */

.equ	 MICR,		(0x40500108)  /* Modem In Control Register */
.equ	 MICR_FEIE,	(1 << 3)	/* FIFO Error */

.equ	 MOSR,		(0x40500110)  /* Modem Out Status Register */
.equ	 MOSR_FIFOE,	(1 << 4)	/* FIFO error */

.equ	 MISR,		(0x40500118)  /* Modem In Status Register */
.equ	 MISR_FIFOE,	(1 << 4)	/* FIFO error */

.equ	 MODR,		(0x40500140)  /* Modem FIFO Data Register */

.equ	 PAC_REG_BASE,	(0x40500200)  /* Primary Audio Codec */
.equ	 SAC_REG_BASE,	(0x40500300)  /* Secondary Audio Codec */
.equ	 PMC_REG_BASE,	(0x40500400)  /* Primary Modem Codec */
.equ	 SMC_REG_BASE,	(0x40500500)  /* Secondary Modem Codec */

/*
 * USB Device Controller
 */
.equ	 UDC_RES1,	(0x40600004)  /* UDC Undocumented - Reserved1 */
.equ	 UDC_RES2,	(0x40600008)  /* UDC Undocumented - Reserved2 */
.equ	 UDC_RES3,	(0x4060000C)  /* UDC Undocumented - Reserved3 */

.equ	 UDCCR,		(0x40600000)  /* UDC Control Register */
.equ	 UDCCR_UDE,	(1 << 0)	/* UDC enable */
.equ	 UDCCR_UDA,	(1 << 1)	/* UDC active */
.equ	 UDCCR_RSM,	(1 << 2)	/* Device resume */
.equ	 UDCCR_RESIR,	(1 << 3)	/* Resume interrupt .equ	est */
.equ	 UDCCR_SUSIR,	(1 << 4)	/* Suspend interrupt .equ	est */
.equ	 UDCCR_SRM,	(1 << 5)	/* Suspend/resume interrupt mask */
.equ	 UDCCR_RSTIR,	(1 << 6)	/* Reset interrupt .equ	est */
.equ	 UDCCR_REM,	(1 << 7)	/* Reset interrupt mask */

.equ	 UDCCS0,		(0x40600010)  /* UDC Endpoint 0 Control/Status Register */
.equ	 UDCCS0_OPR,	(1 << 0)	/* OUT packet ready */
.equ	 UDCCS0_IPR,	(1 << 1)	/* IN packet ready */
.equ	 UDCCS0_FTF,	(1 << 2)	/* Flush Tx FIFO */
.equ	 UDCCS0_DRWF,	(1 << 3)	/* Device remote wakeup feature */
.equ	 UDCCS0_SST,	(1 << 4)	/* Sent stall */
.equ	 UDCCS0_FST,	(1 << 5)	/* Force stall */
.equ	 UDCCS0_RNE,	(1 << 6)	/* Receive FIFO no empty */
.equ	 UDCCS0_SA,	(1 << 7)	/* Setup active */

/* Bulk IN - Endpoint 1,6,11 */
.equ	 UDCCS1,		(0x40600014)  /* UDC Endpoint 1 (IN) Control/Status Register */
.equ	 UDCCS6,		(0x40600028)  /* UDC Endpoint 6 (IN) Control/Status Register */
.equ	 UDCCS11,		(0x4060003C)  /* UDC Endpoint 11 (IN) Control/Status Register */

.equ	 UDCCS_BI_TFS,	(1 << 0)	/* Transmit FIFO service */
.equ	 UDCCS_BI_TPC,	(1 << 1)	/* Transmit packet complete */
.equ	 UDCCS_BI_FTF,	(1 << 2)	/* Flush Tx FIFO */
.equ	 UDCCS_BI_TUR,	(1 << 3)	/* Transmit FIFO underrun */
.equ	 UDCCS_BI_SST,	(1 << 4)	/* Sent stall */
.equ	 UDCCS_BI_FST,	(1 << 5)	/* Force stall */
.equ	 UDCCS_BI_TSP,	(1 << 7)	/* Transmit short packet */

/* Bulk OUT - Endpoint 2,7,12 */
.equ	 UDCCS2,		(0x40600018)  /* UDC Endpoint 2 (OUT) Control/Status Register */
.equ	 UDCCS7,		(0x4060002C)  /* UDC Endpoint 7 (OUT) Control/Status Register */
.equ	 UDCCS12,		(0x40600040)  /* UDC Endpoint 12 (OUT) Control/Status Register */

.equ	 UDCCS_BO_RFS,	(1 << 0)	/* Receive FIFO service */
.equ	 UDCCS_BO_RPC,	(1 << 1)	/* Receive packet complete */
.equ	 UDCCS_BO_DME,	(1 << 3)	/* DMA enable */
.equ	 UDCCS_BO_SST,	(1 << 4)	/* Sent stall */
.equ	 UDCCS_BO_FST,	(1 << 5)	/* Force stall */
.equ	 UDCCS_BO_RNE,	(1 << 6)	/* Receive FIFO not empty */
.equ	 UDCCS_BO_RSP,	(1 << 7)	/* Receive short packet */

/* Isochronous IN - Endpoint 3,8,13 */
.equ	 UDCCS3,		(0x4060001C)  /* UDC Endpoint 3 (IN) Control/Status Register */
.equ	 UDCCS8,		(0x40600030)  /* UDC Endpoint 8 (IN) Control/Status Register */