pxa-regs.inc

一个可以驱动 onenand的代码,使用ADS编译

/*
 *  linux/include/asm-arm/arch-pxa/pxa-regs.h
 *
 *  Author:	Nicolas Pitre
 *  Created:	Jun 15, 2001
 *  Copyright:	MontaVista Software Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * - 2003/01/20: Robert Schwebel <[e-mail]
 *   Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
 *   Added include for hardware.h (for  definition)
 */


.equ	_STACK_BASEADDRESS,	0xa3ff8000
.equ	CFG_MDCNFG_VAL,		0x00000AC8
.equ	CFG_DRAM_BASE,		0xa0000000
/*
 * PXA Chip selects
 */
.equ	PXA_CS0_PHYS,	0x00000000
.equ	PXA_CS1_PHYS,	0x04000000
.equ	PXA_CS2_PHYS,	0x08000000
.equ	PXA_CS3_PHYS,	0x0C000000
.equ	PXA_CS4_PHYS,	0x10000000
.equ	PXA_CS5_PHYS,	0x14000000

/*
 * Personal Computer Memory Card International Association (PCMCIA) sockets
 */
.equ 	PCMCIAPrtSp,	0x04000000	@;/* PCMCIA Partition Space [byte]   */
.equ 	PCMCIASp,	(4*PCMCIAPrtSp) @;/* PCMCIA Space [byte]		   */
.equ 	PCMCIAIOSp,	PCMCIAPrtSp	@;/* PCMCIA I/O Space [byte]	   */
.equ 	PCMCIAAttrSp,	PCMCIAPrtSp	@;/* PCMCIA Attribute Space [byte]   */
.equ 	PCMCIAMemSp,	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]	   */

.equ 	PCMCIA0Sp,	PCMCIASp	/* PCMCIA 0 Space [byte]	   */
.equ 	PCMCIA0IOSp,	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]	   */
.equ	PCMCIA0AttrSp,	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
.equ	PCMCIA0MemSp,	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]	   */

.equ 	PCMCIA1Sp,	PCMCIASp	/* PCMCIA 1 Space [byte]	   */
.equ 	PCMCIA1IOSp,	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]	   */
.equ 	PCMCIA1AttrSp,	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
.equ 	PCMCIA1MemSp,	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]	   */


/*
 * DMA Controller
 */
.equ	 DCSR0,		0x40000000  /* DMA Control / Status Register for Channel 0 */
.equ	 DCSR1,		0x40000004  /* DMA Control / Status Register for Channel 1 */
.equ	 DCSR2,		0x40000008  /* DMA Control / Status Register for Channel 2 */
.equ	 DCSR3,		0x4000000c  /* DMA Control / Status Register for Channel 3 */
.equ	 DCSR4,		0x40000010  /* DMA Control / Status Register for Channel 4 */
.equ	 DCSR5,		0x40000014  /* DMA Control / Status Register for Channel 5 */
.equ	 DCSR6,		0x40000018  /* DMA Control / Status Register for Channel 6 */
.equ	 DCSR7,		0x4000001c  /* DMA Control / Status Register for Channel 7 */
.equ	 DCSR8,		0x40000020  /* DMA Control / Status Register for Channel 8 */
.equ	 DCSR9,		0x40000024  /* DMA Control / Status Register for Channel 9 */
.equ	 DCSR10,	0x40000028  /* DMA Control / Status Register for Channel 10 */
.equ	 DCSR11,	0x4000002c  /* DMA Control / Status Register for Channel 11 */
.equ	 DCSR12,	0x40000030  /* DMA Control / Status Register for Channel 12 */
.equ	 DCSR13,	0x40000034  /* DMA Control / Status Register for Channel 13 */
.equ	 DCSR14,	0x40000038  /* DMA Control / Status Register for Channel 14 */
.equ	 DCSR15,	0x4000003c  /* DMA Control / Status Register for Channel 15 */

@;.equ	 DCSR(x),	(0x40000000 + ((x) << 2))

.equ	 DCSR_RUN,		(1 << 31)	/* Run Bit (read / write) */
.equ	 DCSR_NODESC,		(1 << 30)	/* No-Descriptor Fetch (read / write) */
.equ	 DCSR_STOPIRQEN,	(1 << 29)	/* Stop Interrupt Enable (read / write) */

.equ	 DCSR_EORIRQEN,		(1 << 28)	/* End of Receive Interrupt Enable (R/W) */
.equ	 DCSR_EORJMPEN,		(1 << 27)	/* Jump to next descriptor on EOR */
.equ	 DCSR_EORSTOPEN,	(1 << 26)	/* STOP on an EOR */
.equ	 DCSR_SETCMPST,		(1 << 25)	/* Set Descriptor Compare Status */
.equ	 DCSR_CLRCMPST,		(1 << 24)	/* Clear Descriptor Compare Status */
.equ	 DCSR_CMPST,		(1 << 10)	/* The Descriptor Compare Status */
.equ	 DCSR_ENRINTR,		(1 << 9)	/* The end of Receive */

.equ	 DCSR_REQPEND,		(1 << 8)	/* .equ	est Pending (read-only) */
.equ	 DCSR_STOPSTATE,	(1 << 3)	/* Stop State (read-only) */
.equ	 DCSR_ENDINTR,		(1 << 2)	/* End Interrupt (read / write) */
.equ	 DCSR_STARTINTR,	(1 << 1)	/* Start Interrupt (read / write) */
.equ	 DCSR_BUSERR,		(1 << 0)	/* Bus Error Interrupt (read / write) */

.equ	 DINT,		0x400000f0  /* DMA Interrupt Register */

.equ	 DRCMR0,	0x40000100  /* .equ	est to Channel Map Register for DREQ 0 */
.equ	 DRCMR1,	0x40000104  /* .equ	est to Channel Map Register for DREQ 1 */
.equ	 DRCMR2,	0x40000108  /* .equ	est to Channel Map Register for I2S receive .equ	est */
.equ	 DRCMR3,	0x4000010c  /* .equ	est to Channel Map Register for I2S transmit .equ	est */
.equ	 DRCMR4,	0x40000110  /* .equ	est to Channel Map Register for BTUART receive .equ	est */
.equ	 DRCMR5,	0x40000114  /* .equ	est to Channel Map Register for BTUART transmit .equ	est. */
.equ	 DRCMR6,	0x40000118  /* .equ	est to Channel Map Register for FFUART receive .equ	est */
.equ	 DRCMR7,	0x4000011c  /* .equ	est to Channel Map Register for FFUART transmit .equ	est */
.equ	 DRCMR8,	0x40000120  /* .equ	est to Channel Map Register for AC97 microphone .equ	est */
.equ	 DRCMR9,	0x40000124  /* .equ	est to Channel Map Register for AC97 modem receive .equ	est */
.equ	 DRCMR10,	0x40000128  /* .equ	est to Channel Map Register for AC97 modem transmit .equ	est */
.equ	 DRCMR11,	0x4000012c  /* .equ	est to Channel Map Register for AC97 audio receive .equ	est */
.equ	 DRCMR12,	0x40000130  /* .equ	est to Channel Map Register for AC97 audio transmit .equ	est */
.equ	 DRCMR13,	0x40000134  /* .equ	est to Channel Map Register for SSP receive .equ	est */
.equ	 DRCMR14,	0x40000138  /* .equ	est to Channel Map Register for SSP transmit .equ	est */
.equ	 DRCMR15,	0x4000013c  /* Reserved */
.equ	 DRCMR16,	0x40000140  /* Reserved */
.equ	 DRCMR17,	0x40000144  /* .equ	est to Channel Map Register for ICP receive .equ	est */
.equ	 DRCMR18,	0x40000148  /* .equ	est to Channel Map Register for ICP transmit .equ	est */
.equ	 DRCMR19,	0x4000014c  /* .equ	est to Channel Map Register for STUART receive .equ	est */
.equ	 DRCMR20,	0x40000150  /* .equ	est to Channel Map Register for STUART transmit .equ	est */
.equ	 DRCMR21,	0x40000154  /* .equ	est to Channel Map Register for MMC receive .equ	est */
.equ	 DRCMR22,	0x40000158  /* .equ	est to Channel Map Register for MMC transmit .equ	est */
.equ	 DRCMR23,	0x4000015c  /* Reserved */
.equ	 DRCMR24,	0x40000160  /* Reserved */
.equ	 DRCMR25,	0x40000164  /* .equ	est to Channel Map Register for USB endpoint 1 .equ	est */
.equ	 DRCMR26,	0x40000168  /* .equ	est to Channel Map Register for USB endpoint 2 .equ	est */
.equ	 DRCMR27,	0x4000016C  /* .equ	est to Channel Map Register for USB endpoint 3 .equ	est */
.equ	 DRCMR28,	0x40000170  /* .equ	est to Channel Map Register for USB endpoint 4 .equ	est */
.equ	 DRCMR29,	0x40000174  /* Reserved */
.equ	 DRCMR30,	0x40000178  /* .equ	est to Channel Map Register for USB endpoint 6 .equ	est */
.equ	 DRCMR31,	0x4000017C  /* .equ	est to Channel Map Register for USB endpoint 7 .equ	est */
.equ	 DRCMR32,	0x40000180  /* .equ	est to Channel Map Register for USB endpoint 8 .equ	est */
.equ	 DRCMR33,	0x40000184  /* .equ	est to Channel Map Register for USB endpoint 9 .equ	est */
.equ	 DRCMR34,	0x40000188  /* Reserved */
.equ	 DRCMR35,	0x4000018C  /* .equ	est to Channel Map Register for USB endpoint 11 .equ	est */
.equ	 DRCMR36,	0x40000190  /* .equ	est to Channel Map Register for USB endpoint 12 .equ	est */
.equ	 DRCMR37,	0x40000194  /* .equ	est to Channel Map Register for USB endpoint 13 .equ	est */
.equ	 DRCMR38,	0x40000198  /* .equ	est to Channel Map Register for USB endpoint 14 .equ	est */
.equ	 DRCMR39,	0x4000019C  /* Reserved */

.equ	 DRCMR68,	0x40001110  /* .equ	est to Channel Map Register for Camera FIFO 0 .equ	est */
.equ	 DRCMR69,	0x40001114  /* .equ	est to Channel Map Register for Camera FIFO 1 .equ	est */
.equ	 DRCMR70,	0x40001118  /* .equ	est to Channel Map Register for Camera FIFO 2 .equ	est */

.equ	 DRCMRRXSADR,	DRCMR2
.equ	 DRCMRTXSADR,	DRCMR3
.equ	 DRCMRRXBTRBR,	DRCMR4
.equ	 DRCMRTXBTTHR,	DRCMR5
.equ	 DRCMRRXFFRBR,	DRCMR6
.equ	 DRCMRTXFFTHR,	DRCMR7
.equ	 DRCMRRXMCDR,	DRCMR8
.equ	 DRCMRRXMODR,	DRCMR9
.equ	 DRCMRTXMODR,	DRCMR10
.equ	 DRCMRRXPCDR,	DRCMR11
.equ	 DRCMRTXPCDR,	DRCMR12
.equ	 DRCMRRXSSDR,	DRCMR13
.equ	 DRCMRTXSSDR,	DRCMR14
.equ	 DRCMRRXICDR,	DRCMR17
.equ	 DRCMRTXICDR,	DRCMR18
.equ	 DRCMRRXSTRBR,	DRCMR19
.equ	 DRCMRTXSTTHR,	DRCMR20
.equ	 DRCMRRXMMC,	DRCMR21
.equ	 DRCMRTXMMC,	DRCMR22

.equ	 DRCMR_MAPVLD,	(1 << 7)	/* Map Valid (read / write) */
.equ	 DRCMR_CHLNUM,	0x0f		/* mask for Channel Number (read / write) */

.equ	 DDADR0,	0x40000200  /* DMA Descriptor Address Register Channel 0 */
.equ	 DSADR0,	0x40000204  /* DMA Source Address Register Channel 0 */
.equ	 DTADR0,	0x40000208  /* DMA Target Address Register Channel 0 */
.equ	 DCMD0,		0x4000020c  /* DMA Command Address Register Channel 0 */
.equ	 DDADR1,	0x40000210  /* DMA Descriptor Address Register Channel 1 */
.equ	 DSADR1,	0x40000214  /* DMA Source Address Register Channel 1 */
.equ	 DTADR1,	0x40000218  /* DMA Target Address Register Channel 1 */
.equ	 DCMD1,		0x4000021c  /* DMA Command Address Register Channel 1 */
.equ	 DDADR2,	0x40000220  /* DMA Descriptor Address Register Channel 2 */
.equ	 DSADR2,	0x40000224  /* DMA Source Address Register Channel 2 */
.equ	 DTADR2,	0x40000228  /* DMA Target Address Register Channel 2 */
.equ	 DCMD2,		0x4000022c  /* DMA Command Address Register Channel 2 */
.equ	 DDADR3,	0x40000230  /* DMA Descriptor Address Register Channel 3 */
.equ	 DSADR3,	0x40000234  /* DMA Source Address Register Channel 3 */
.equ	 DTADR3,	0x40000238  /* DMA Target Address Register Channel 3 */
.equ	 DCMD3,		0x4000023c  /* DMA Command Address Register Channel 3 */
.equ	 DDADR4,	0x40000240  /* DMA Descriptor Address Register Channel 4 */
.equ	 DSADR4,	0x40000244  /* DMA Source Address Register Channel 4 */
.equ	 DTADR4,	0x40000248  /* DMA Target Address Register Channel 4 */
.equ	 DCMD4,		0x4000024c  /* DMA Command Address Register Channel 4 */
.equ	 DDADR5,	0x40000250  /* DMA Descriptor Address Register Channel 5 */
.equ	 DSADR5,	0x40000254  /* DMA Source Address Register Channel 5 */
.equ	 DTADR5,	0x40000258  /* DMA Target Address Register Channel 5 */
.equ	 DCMD5,		0x4000025c  /* DMA Command Address Register Channel 5 */
.equ	 DDADR6,	0x40000260  /* DMA Descriptor Address Register Channel 6 */
.equ	 DSADR6,	0x40000264  /* DMA Source Address Register Channel 6 */
.equ	 DTADR6,	0x40000268  /* DMA Target Address Register Channel 6 */
.equ	 DCMD6,		0x4000026c  /* DMA Command Address Register Channel 6 */
.equ	 DDADR7,	0x40000270  /* DMA Descriptor Address Register Channel 7 */
.equ	 DSADR7,	0x40000274  /* DMA Source Address Register Channel 7 */
.equ	 DTADR7,	0x40000278  /* DMA Target Address Register Channel 7 */
.equ	 DCMD7,		0x4000027c  /* DMA Command Address Register Channel 7 */
.equ	 DDADR8,	0x40000280  /* DMA Descriptor Address Register Channel 8 */
.equ	 DSADR8,	0x40000284  /* DMA Source Address Register Channel 8 */
.equ	 DTADR8,	0x40000288  /* DMA Target Address Register Channel 8 */
.equ	 DCMD8,		0x4000028c  /* DMA Command Address Register Channel 8 */
.equ	 DDADR9,	0x40000290  /* DMA Descriptor Address Register Channel 9 */
.equ	 DSADR9,	0x40000294  /* DMA Source Address Register Channel 9 */
.equ	 DTADR9,	0x40000298  /* DMA Target Address Register Channel 9 */
.equ	 DCMD9,		0x4000029c  /* DMA Command Address Register Channel 9 */
.equ	 DDADR10,	0x400002a0  /* DMA Descriptor Address Register Channel 10 */
.equ	 DSADR10,	0x400002a4  /* DMA Source Address Register Channel 10 */
.equ	 DTADR10,	0x400002a8  /* DMA Target Address Register Channel 10 */
.equ	 DCMD10,	0x400002ac  /* DMA Command Address Register Channel 10 */
.equ	 DDADR11,	0x400002b0  /* DMA Descriptor Address Register Channel 11 */
.equ	 DSADR11,	0x400002b4  /* DMA Source Address Register Channel 11 */
.equ	 DTADR11,	0x400002b8  /* DMA Target Address Register Channel 11 */
.equ	 DCMD11,	0x400002bc  /* DMA Command Address Register Channel 11 */
.equ	 DDADR12,	0x400002c0  /* DMA Descriptor Address Register Channel 12 */
.equ	 DSADR12,	0x400002c4  /* DMA Source Address Register Channel 12 */
.equ	 DTADR12,	0x400002c8  /* DMA Target Address Register Channel 12 */
.equ	 DCMD12,	0x400002cc  /* DMA Command Address Register Channel 12 */
.equ	 DDADR13,	0x400002d0  /* DMA Descriptor Address Register Channel 13 */
.equ	 DSADR13,	0x400002d4  /* DMA Source Address Register Channel 13 */
.equ	 DTADR13,	0x400002d8  /* DMA Target Address Register Channel 13 */
.equ	 DCMD13,	0x400002dc  /* DMA Command Address Register Channel 13 */
.equ	 DDADR14,	0x400002e0  /* DMA Descriptor Address Register Channel 14 */
.equ	 DSADR14,	0x400002e4  /* DMA Source Address Register Channel 14 */
.equ	 DTADR14,	0x400002e8  /* DMA Target Address Register Channel 14 */
.equ	 DCMD14,	0x400002ec  /* DMA Command Address Register Channel 14 */
.equ	 DDADR15,	0x400002f0  /* DMA Descriptor Address Register Channel 15 */
.equ	 DSADR15,	0x400002f4  /* DMA Source Address Register Channel 15 */
.equ	 DTADR15,	0x400002f8  /* DMA Target Address Register Channel 15 */
.equ	 DCMD15,	0x400002fc  /* DMA Command Address Register Channel 15 */

@;.equ	 DDADR(x),	(0x40000200, (x) << 4)
@;.equ	 DSADR(x),	(0x40000204, (x) << 4)
@;.equ	 DTADR(x),	(0x40000208, (x) << 4)
@;.equ	 DCMD(x),	(0x4000020c, (x) << 4)

.equ	 DDADR_DESCADDR,	0xfffffff0	/* Address of next descriptor (mask) */
.equ	 DDADR_STOP,		(1 << 0)	/* Stop (read / write) */

.equ	 DCMD_INCSRCADDR, 	(1 << 31)	/* Source Address Increment Setting. */
.equ	 DCMD_INCTRGADDR, 	(1 << 30)	/* Target Address Increment Setting. */
.equ	 DCMD_FLOWSRC,		(1 << 29)	/* Flow Control by the source. */
.equ	 DCMD_FLOWTRG,		(1 << 28)	/* Flow Control by the target. */
.equ	 DCMD_STARTIRQEN, 	(1 << 22)	/* Start Interrupt Enable */
.equ	 DCMD_ENDIRQEN,		(1 << 21)	/* End Interrupt Enable */
.equ	 DCMD_ENDIAN,		(1 << 18)	/* Device Endian-ness. */
.equ	 DCMD_BURST8,		(1 << 16)	/* 8 byte burst */
.equ	 DCMD_BURST16,		(2 << 16)	/* 16 byte burst */
.equ	 DCMD_BURST32,		(3 << 16)	/* 32 byte burst */
.equ	 DCMD_WIDTH1,		(1 << 14)	/* 1 byte width */
.equ	 DCMD_WIDTH2,		(2 << 14)	/* 2 byte width (HalfWord) */
.equ	 DCMD_WIDTH4,		(3 << 14)	/* 4 byte width (Word) */
.equ	 DCMD_LENGTH,		0x01fff		/* length mask (max = 8K - 1) */

/* default combinations */
.equ	 DCMD_RXPCDR,	(DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
.equ	 DCMD_RXMCDR,	(DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
.equ	 DCMD_TXPCDR,	(DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)

/*
 * UARTs
 */
/* Full Function UART (FFUART) */
.equ	 FFUART,	FFRBR
.equ	 FFRBR,		(0x40100000)  /* Receive Buffer Register (read only) */
.equ	 FFTHR,		(0x40100000)  /* Transmit Holding Register (write only) */
.equ	 FFIER,		(0x40100004)  /* Interrupt Enable Register (read/write) */
.equ	 FFIIR,		(0x40100008)  /* Interrupt ID Register (read only) */
.equ	 FFFCR,		(0x40100008)  /* FIFO Control Register (write only) */
.equ	 FFLCR,		(0x4010000C)  /* Line Control Register (read/write) */
.equ	 FFMCR,		(0x40100010)  /* Modem Control Register (read/write) */
.equ	 FFLSR,		(0x40100014)  /* Line Status Register (read only) */
.equ	 FFMSR,		(0x40100018)  /* Modem Status Register (read only) */
.equ	 FFSPR,		(0x4010001C)  /* Scratch Pad Register (read/write) */
.equ	 FFISR,		(0x40100020)  /* Infrared Selection Register (read/write) */
.equ	 FFDLL,		(0x40100000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
.equ	 FFDLH,		(0x40100004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */

/* Bluetooth UART (BTUART) */
.equ	 BTUART,	BTRBR
.equ	 BTRBR,		(0x40200000)  /* Receive Buffer Register (read only) */
.equ	 BTTHR,		(0x40200000)  /* Transmit Holding Register (write only) */
.equ	 BTIER,		(0x40200004)  /* Interrupt Enable Register (read/write) */
.equ	 BTIIR,		(0x40200008)  /* Interrupt ID Register (read only) */
.equ	 BTFCR,		(0x40200008)  /* FIFO Control Register (write only) */
.equ	 BTLCR,		(0x4020000C)  /* Line Control Register (read/write) */