uart.vhd

UART控制器,可以实现异步通用串行输入输出的控制

	
	--idle status
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Is_Rx_idle<='1';
		elsif (Clk'event and Clk='1') then
			if (Is_Rx_idle='1' and Is_SOF_detct='1') then
				Is_Rx_idle<='0';
				RXE_sample<=RXE;
			elsif (Is_Rx_Over='1') then
				Is_Rx_idle<='1';
			end if;
		end if;
	end process;
	
	--SOF status
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Is_Rx_SOF<='0';
			rxClk1<='0';
		elsif (Clk'event and Clk='1') then 
			Is_Rx_idle1<=Is_Rx_idle; 
			rxClk1<=rxClk;
			if (Is_Rx_idle1='1' and Is_Rx_idle='0') then
				Is_Rx_SOF<='1';
			elsif (rxClk1<='0' and rxClk='1' and Is_Rx_SOF='1') then
				Is_Rx_SOF<='0';
			end if;
		end if;
	end process;
	
	--Dat status
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Is_Rx_Dat<='0';
			rxClk2<='0';
			Is_Rx_SOF1<='0';
		elsif (Clk'event and Clk='1') then
			Is_Rx_SOF1<=Is_Rx_SOF;
			rxClk2<=rxClk;
			if (Is_Rx_SOF1='1' and Is_Rx_SOF='0') then
				Is_Rx_Dat<='1';
				Rx_CL<=0;
			elsif (Rx_CL=Uart_CL and Is_Rx_Dat='1') then
				Is_Rx_Dat<='0';
			elsif (rxClk2<='0' and rxClk='1') then
				Rx_CL<=Rx_CL+1;
			end if;
		end if;
	end process;
	
	
	--Rx_Parity status
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Is_Rx_Parity<='0';
			rxClk3<='0';
			Is_Rx_Dat1<='0';
		elsif (Clk'event and Clk='1') then
			Is_Rx_Dat1<=Is_Rx_Dat;
			rxClk3<=rxClk;
			if (Uart_PEN=1 and Is_Rx_Dat1='1' and Is_Rx_Dat='0') then
				Is_Rx_Parity<='1';
			elsif (rxClk='1' and rxClk3='0' and Is_Rx_Parity='1') then
				Is_Rx_Parity<='0';
			end if;
		end if;
	end process;
	
	--EOF status
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Is_Rx_EOF<='0';
			rxClk4<='0';
			Is_Rx_Parity1<='0';
			Is_Rx_Dat2<='0';
			Rx_SBL<=Uart_SBL;
		elsif (Clk'event and Clk='1') then
			rxClk4<=rxClk;
			Is_Rx_Parity1<=Is_Rx_Parity;
			Is_Rx_Dat2<=Is_Rx_Dat;
			if ((Uart_PEN=1 and Is_Rx_Parity1='1' and Is_Rx_Parity='0')or(Uart_PEN=0 and Is_Rx_Dat2='1' and Is_Rx_Dat='0')) then
				Is_Rx_EOF<='1';
				Rx_SBL<=0;
			elsif (Rx_SBL=Uart_SBL and Is_Rx_EOF='1') then
				Is_Rx_EOF<='0';
			elsif (rxClk4='0' and rxClk='1') then
				Rx_SBL<=Rx_SBL+1;
			end if;
		end if;
	end process;
	
	--Rx Over
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Is_Rx_Over<='0';
			Is_Rx_EOF1<='0';
		elsif (Clk'event and Clk='1') then
			Is_Rx_EOF1<=Is_Rx_EOF;
			if (Is_Rx_EOF1='1' and Is_Rx_EOF='0') then
				Is_Rx_Over<='1';
			else
				Is_Rx_Over<='0';
			end if;
		end if;
	end process;
	
	--output error flag
	process(Clk,RstH)
	begin
		if (RstH='1') then
			PE<='0';
			FRE<='0';
		elsif (Clk'event and Clk='1') then
			if (REC='1') then
				PE<='0';
				FRE<='0';
			elsif (Is_Rx_Over='1') then
				PE<=Is_Parity_Err;
				FRE<=Is_SOF_Err or Is_EOF_Err;
			end if;
		end if;
	end process;
	
	----------------------------------------------------------------------------------------
	--			Transmit
	-----------------------------------------------------------------------------------------
	--write date will be transmitted into TD_Reg(transmit data register) when it is empty
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Is_TD_Reg_Empty<='1';
		elsif (Clk'event and Clk='1') then
			if (Is_TD_Reg_Empty='1' and WR='1') then
				TD_Reg<=SODR;
				Is_TD_Reg_Empty<='0';
			elsif (Is_Tx_Start='1') then
				Is_TD_Reg_Empty<='1';
			end if;
		end if;
	end process;
	
	--tx idle status
	process(Clk,RstH)
a	begin
		if (RstH='1') then
			Is_Tx_idle<='1';
			Is_Tx_Start<='0';
		elsif (Clk'event and Clk='1') then
			if (Is_Tx_idle='1' and Is_TD_Reg_Empty='0' and TXE='1') then
				Is_Tx_idle<='0';
				Is_Tx_Start<='1';
			elsif(Is_Tx_Over='1') then
				Is_Tx_idle<='1';
				Is_Tx_Start<='0';
			else
				Is_Tx_Start<='0';
			end if;
		end if;
	end process;
			
	--tx Clock
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Tx_Clk<='0';
			SysClk_Div_Tx<=0;
		elsif (Clk'event and Clk='1') then
			if (Is_Tx_Start='1') then
				SysClk_Div_Tx<=0;
				Tx_Clk<='0';
			elsif (SysClk_Div_Tx=Uart_SysClk_Div2-1) then
				SysClk_Div_Tx<=0;
				Tx_Clk<='1';
			else
				SysClk_Div_Tx<=SysClk_Div_Tx+1;
				Tx_Clk<='0';
			end if;
		end if;
	end process;
	
	--tx SOF status
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Is_Tx_SOF<='0';
		elsif (Clk'event and Clk='1') then
			if (Is_Tx_Start='1') then
				Is_Tx_SOF<='1';
			elsif(Tx_Clk='1' and Is_Tx_SOF='1') then
				Is_Tx_SOF<='0';
			end if;
		end if;
	end process;
	
	--tx data status
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Is_Tx_Dat<='0';
			Is_Tx_SOF1<='0';
			Tx_CL<=0;
		elsif (Clk'event and Clk='1') then
			Is_Tx_SOF1<=Is_Tx_SOF;
			if (Is_Tx_SOF='0' and Is_Tx_SOF1='1') then
				Is_Tx_Dat<='1';
				Tx_CL<=0;
			elsif (Tx_CL=Uart_CL and Is_Tx_Dat='1') then
				Is_Tx_Dat<='0';
			elsif (Tx_Clk='1') then
				Tx_CL<=Tx_CL+1;
			end if;
		end if;
	end process;
	
	--tx parity status
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Is_Tx_Parity<='0';
			Is_Tx_Dat1<='0';
		elsif (Clk'event and Clk='1') then
			Is_Tx_Dat1<=Is_Tx_Dat;
			if (Is_Tx_Dat1='1' and Is_Tx_Dat='0' and Uart_PEN=1) then
				Is_Tx_Parity<='1';
			elsif (Tx_Clk='1' and Is_Tx_Parity='1') then
				Is_Tx_Parity<='0';
			end if;
		end if;
	end process;
	
	--tx EOF status
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Is_Tx_EOF<='0';
			Is_Tx_Dat2<='0';
			Is_Tx_Parity1<='0';
			Tx_SBL<=0;
		elsif (Clk'event and Clk='1') then
			Is_Tx_Dat2<=Is_Tx_Dat;
			Is_Tx_Parity1<=Is_Tx_Parity;
			if ((Uart_PEN=1 and Is_Tx_Parity1='1' and Is_Tx_Parity='0') or (Uart_PEN=0 and Is_Tx_Dat2='1' and Is_Tx_Dat='0')) then
				Is_Tx_EOF<='1';
				Tx_SBL<=0;
			elsif (Tx_SBL=Uart_SBL and Is_Tx_EOF='1') then
				Is_Tx_EOF<='0';
			elsif (Tx_Clk='1') then
				Tx_SBL<=Tx_SBL+1;
			end if;
		end if;
	end process;
	
	
	--tx is over
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Is_Tx_Over<='0';
			Is_Tx_EOF1<='0';
		elsif(Clk'event and Clk='1') then
			Is_Tx_EOF1<=Is_Tx_EOF;
			if (Is_Tx_EOF1='1' and Is_Tx_EOF='0') then
				Is_Tx_Over<='1';
			else
				Is_Tx_Over<='0';
			end if;
		end if;
	end process;
	
	--calculate parity and shift Tx_Shifter
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Tx_Parity<=Uart_P;
		elsif (Clk'event and Clk='1') then
			if (Is_Tx_Start='1') then
				Tx_Shifer<=TD_Reg;
				Tx_Parity<=Uart_P xor TD_Reg(0);
			elsif (Is_Tx_Dat='1' and Tx_Clk='1') then
				Tx_Shifer(Uart_CL-2 downto 0)<=Tx_Shifer(Uart_CL-1 downto 1);
				Tx_Parity<=Tx_Parity xor Tx_Shifer(0);
			end if;
		end if;
	end process;

	--output data serially
	process(Clk,RstH)
	begin
		if (RstH='1') then
			SOT<='1';
		elsif (Clk'event and Clk='1') then
			if (Is_Tx_idle='1') then
				SOT<='1';
			elsif (Is_Tx_SOF='1') then
				SOT<='0';
			elsif(Is_Tx_Dat='1') then
				SOT<=Tx_Shifer(0);
			elsif (Is_Tx_Parity='1') then
				SOT<=Tx_Parity;
			elsif (Is_Tx_EOF='1') then
				SOT<='1';
			end if;
		end if;
	end process;
	
	TDRE<=Is_TD_Reg_Empty;
		
		
	--sample<=sampleClk;		--just dbg
	--rxclock<=rxClk;			--just dbg
	--Update<=Is_Sample_Updated;      --just dbg
	--shift<=Rx_Shifter;                 --just dbg
	--is_idle<=Is_Rx_idle;
	--is_SOF<=Is_Rx_SOF;
	--is_Dat<=Is_Rx_Dat;
	--is_parity<=Is_Rx_Parity;
	--is_EOF<=Is_Rx_EOF;
	--is_Over<=Is_Rx_Over;
	--
	--is_Txidle<=Is_Tx_idle;
	--is_TxSOF<=Is_Tx_SOF;
	--is_TxDat<=Is_Tx_Dat;
	--is_TxParity<=Is_Tx_Parity;
	--is_TxEOF<=Is_Tx_EOF;
end RTL;