uart.vhd

UART控制器,可以实现异步通用串行输入输出的控制

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.Uart_Cfg.all;

entity Uart is
	port
	(
		RstH	:	in	std_logic;				--high level available
		Clk	:	in	std_logic;				--system clock
		SIN	:	in	std_logic;				--serial input
		SOT	:	out	std_logic;				--serial output
		TXE	:	in	std_logic;				--transmit enable
		RXE	:	in	std_logic;				--receiver enable
		PE	:	out	std_logic;				--Rx_Parity error
		FRE	:	out	std_logic;				--framing error
		ORE	:	out	std_logic;				--overrun error
		REC	:	in	std_logic;				--receiver error clear
		RDRF	:	out	std_logic;				--receiver data register full
		TDRE	:	out	std_logic;				--transmit data register empty
		SIDR	:	out	std_logic_vector(Uart_CL-1 downto 0);	--serial input data register
		SODR	:	in	std_logic_vector(Uart_CL-1 downto 0);	--serial output data register
		RD	:	in	std_logic;				--read SIDR
		WR	:	in	std_logic				--write SODR
		
		--;
		--sample	:	out	std_logic;
		--rxclock :	out	std_logic;
		--Update	:	out	std_logic;
		--shift	:	out	std_logic_vector(Uart_CL-1 downto 0);
		--is_idle	:	out	std_logic;
		--is_SOF	:	out	std_logic;
		--is_Dat	:	out	std_logic;
		--is_parity:	out	std_logic;
		--is_EOF	:	out	std_logic;
		--is_Over	:	out	std_logic;
		--is_Txidle:	out	std_logic;
		--is_TxSOF:       out	std_logic;
		--is_TxDat:       out	std_logic;
		--is_TxParity:    out	std_logic;
		--is_TxEOF:       out	std_logic
	);
end Uart;

architecture RTL of Uart is

--------------------------------------------------------------------------------------------------
--Signal for receiver
--------------------------------------------------------------------------------------------------
signal Is_Rx_idle	:	std_logic;
signal Is_Rx_SOF	:	std_logic;
signal Is_Rx_Dat	:	std_logic;
signal Is_Rx_Parity	:	std_logic;
signal Is_Rx_EOF	:	std_logic;
signal Is_Rx_Over	:	std_logic;

signal Is_Rx_idle1	:	std_logic;
signal Is_Rx_SOF1	:	std_logic;
signal Is_Rx_Dat1	:	std_logic;
signal Is_Rx_Dat2	:	std_logic;
signal Is_Rx_Parity1	:	std_logic;
signal Is_Rx_EOF1	:	std_logic;

signal Rx_CL		:	integer:=Uart_CL;
signal Rx_SBL		:	integer:=Uart_SBL;
signal RXE_sample	:	std_logic;

signal Is_SOF_detct	:	std_logic;

signal sysClk_div	:	integer:=Uart_SysClk_Div;
signal sampleClk_div	:	std_logic_vector(3 downto 0);
signal sampleClk	:	std_logic;
signal rxClk		:	std_logic;

signal rxClk1		:	std_logic;
signal rxClk2		:	std_logic;
signal rxClk3		:	std_logic;
signal rxClk4		:	std_logic;

signal Is_Sample_Updated:	std_logic;
signal Sample1		:	std_logic;
signal Sample2		:	std_logic;
signal Sample3		:	std_logic;
signal SampleRx		:	std_logic;

signal Rx_Shifter	:	std_logic_vector(Uart_CL-1 downto 0);
signal Sample_Updated_1	:	std_logic;

signal RD_Reg		:	std_logic_vector(Uart_CL-1 downto 0);

signal Is_Rx_Err	:	std_logic;
signal Is_SOF_Err	:	std_logic;
signal Is_EOF_Err	:	std_logic;
signal Is_Parity_Err	:	std_logic;
signal Rx_Parity	:	std_logic;
signal Not_Read		:	std_logic;
signal Sample_Updated_2	:	std_logic;
signal Sample_Updated_3	:	std_logic;
signal Sample_Updated_4	:	std_logic;

--------------------------------------------------------------------------------------------------
--Signal for transmiter
--------------------------------------------------------------------------------------------------
signal Is_TD_Reg_Empty	:	std_logic;
signal Is_Tx_idle	:	std_logic;
signal Is_Tx_SOF	:	std_logic;
signal Is_Tx_Dat	:	std_logic;
signal Is_Tx_Parity	:	std_logic;
signal Is_Tx_EOF	:	std_logic;
signal Is_Tx_Over	:	std_logic;

signal Is_Tx_SOF1	:	std_logic;
signal Is_Tx_Dat1	:	std_logic;
signal Is_Tx_Dat2	:	std_logic;
signal Is_Tx_Parity1	:	std_logic;
signal Is_Tx_EOF1	:	std_logic;

signal TD_Reg		:	std_logic_vector(Uart_CL-1 downto 0);
signal Tx_Shifer	:	std_logic_vector(Uart_CL-1 downto 0);

signal SysClk_Div_Tx	:	integer:=Uart_SysClk_Div2;
signal Tx_Clk		:	std_logic;

signal Is_Tx_Start	:	std_logic;

signal Tx_CL		:	integer:=Uart_CL;
signal Tx_SBL		:	integer:=Uart_SBL;

signal Tx_Parity	:	std_logic;
begin
	--------------------------------------------------------------------------------
	--		Receiver
	--------------------------------------------------------------------------------
	--detect the "falling edge" of SIN
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Is_SOF_detct<='0';
			--SOF0<='1';
		elsif(Clk'event and Clk='1') then
			--SOF0<=SIN;
			if (SIN='0' and Is_Rx_idle='1') then
				Is_SOF_detct<='1';
			else
				Is_SOF_detct<='0';
			end if;
		end if;
	end process;
	
	--generate the sample clock
	process(Clk,RstH)
	begin
		if (RstH='1') then
			sysClk_div<=0;
			sampleClk<='0';
		elsif(Clk'event and Clk='1') then
			if (Is_Rx_idle='1' and Is_SOF_detct='1') then
				sysClk_div<=0;
				sampleClk<='0';
			elsif (sysClk_div=Uart_SysClk_Div-1) then
				sysClk_div<=0;
				sampleClk<='1';
			else
				sysClk_div<=sysClk_div+1;
				sampleClk<='0';
			end if;
		end if;
	end process;
	
	--generate the rx clock
	process(Clk,RstH)
	begin
		if (RstH='1') then
			sampleClk_div<="1111";
			rxClk<='0';
		elsif(Clk'event and Clk='1') then
			if (Is_Rx_idle='1' and Is_SOF_detct='1') then
				sampleClk_div<="1111";
				rxClk<='1';
			elsif (sampleClk='1') then
				if (sampleClk_div=0) then
					sampleClk_div<="1111";
					rxClk<='1';
				else
					sampleClk_div<=sampleClk_div-"0001";
					rxClk<='0';
				end if;
			end if;
		end if;
	end process;
	
	--sample sin
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Is_Sample_Updated<='0';
		elsif(Clk'event and Clk='1') then
			if (sampleClk_div="1001") then
				Sample1<=SIN;
			elsif (sampleClk_div="1000") then
				Sample2<=SIN;
			elsif (sampleClk_div="0111") then
				Sample3<=SIN;
			elsif (sampleClk_div="0110") then
				Is_Sample_Updated<='1';
			else
				Is_Sample_Updated<='0';
			end if;
		end if;
	end process;
	SampleRx<=Sample2 when ((Sample1=Sample2) or (Sample2=Sample3)) else Sample1;
	
	--receiver shift register.
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Rx_Shifter<=(others=>'0');
			Sample_Updated_1<='0';
		elsif(Clk'event and Clk='1') then
			Sample_Updated_1<=Is_Sample_Updated;
			if (Is_Rx_Dat='1' and Is_Sample_Updated='1' and Sample_Updated_1='0' and RXE_sample='1') then
				Rx_Shifter(Uart_CL-1) <=SampleRx;
				Rx_Shifter(Uart_CL-2 downto 0)<=Rx_Shifter(Uart_CL-1 downto 1);
			end if;
		end if;
	end process;
	
	
                                                                                                                                                                                                                                	
	--receiver data register full
	process(Clk,RstH)
	begin
		if (RstH='1') then
			RDRF<='0';
			SIDR<=(others=>'0');
			RD_Reg<=(others=>'0');
		elsif(Clk'event and Clk='1') then
			if (Is_Rx_Over='1' and Is_Rx_Err='0' and RXE_sample='1') then
				RDRF<='1';
				RD_Reg<=Rx_Shifter;
			elsif (RD='1') then
				RDRF<='0';
			end if;
			
			if (RD='1') then
				SIDR<=RD_Reg;
			end if;
		end if;
	end process;
	Is_Rx_Err<=Is_SOF_Err or Is_EOF_Err or Is_Parity_Err;
	
	--detect SOF error
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Is_SOF_Err<='0';
			Sample_Updated_2<='0';
		elsif (Clk'event and Clk='1') then
			Sample_Updated_2<=Is_Sample_Updated;
			if (REC='1') then
				Is_SOF_Err<='0';
			elsif (Is_Rx_SOF='1' and Sample_Updated_2='0' and Is_Sample_Updated='1' and SampleRx='1' and RXE_sample='1') then
					Is_SOF_Err<='1';
			end if;
		end if;
	end process;
	
	--detect EOF error
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Is_EOF_Err<='0';
			Sample_Updated_3<='0';
		elsif (Clk'event and Clk='1') then
			Sample_Updated_3<=Is_Sample_Updated;
			if (REC='1') then
				Is_EOF_Err<='0';
			elsif (Is_Rx_EOF='1' and Sample_Updated_3='0' and Is_Sample_Updated='1' and SampleRx='0' and RXE_sample='1') then
					Is_EOF_Err<='1';
			end if;
		end if;
	end process;
	
	--detect Rx_Parity error 
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Is_Parity_Err<='0';
			Sample_Updated_4<='0';
			Rx_Parity<=Uart_P;
    		elsif (Clk'event and Clk='1') then
			Sample_Updated_4<=Is_Sample_Updated;
			if (REC='1') then
				Is_Parity_Err<='0';
			elsif (Sample_Updated_4='0' and Is_Sample_Updated='1' and RXE_sample='1') then
				if (Is_Rx_SOF='1') then
					Rx_Parity<=Uart_P;
				elsif (Is_Rx_Parity='1' and Rx_Parity=SampleRx) then
					Is_Parity_Err<='1';
				else
					Rx_Parity<=Rx_Parity xor SampleRx;
				end if;
			end if;
		end if;
	end process;
	
	--detect overrun err;
	process(Clk,RstH)
	begin
		if (RstH='1') then
			ORE<='0';
		elsif (Clk'event and Clk='1') then
			if (REC='1') then
				ORE<='0';
			elsif (Is_Rx_Over='1' and Not_Read='1' and RD='0' and RXE_sample='1') then
				ORE<='1';
			end if;
		end if;
	end process;
	
	--have data in RD_Reg been read?
	process(Clk,RstH)
	begin
		if (RstH='1') then
			Not_Read<='0';
		elsif (Clk'event and Clk='1') then
			if (RD='1') then
				Not_Read<='0';
			elsif (Is_Rx_Over='1' and RXE_sample='1') then
				Not_Read<='1';
			end if;
		end if;
	end process;