uart_config.vhd

来自「UART控制器,可以实现异步通用串行输入输出的控制」· VHDL 代码 · 共 15 行

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

package Uart_Cfg is
	constant Uart_BPS	:	integer :=57600;	--Buad per second.
	constant Uart_CL	:	integer :=8;		--Character length.
	constant Uart_SBL	:	integer :=1;		--Stop bit length.
	constant Uart_PEN	:	integer :=0;		--Parity enable;1 is enable,0 is disable.
	constant Uart_P		:	std_logic :='1';	--Parity;'0' is even parity,'1' is odd parity.
	constant SystemFreq	:	integer	:=40000000;	--system freqency.
	constant Uart_SysClk_Div:	integer	:=SystemFreq/(Uart_BPS*16);--Divisor of systemclock(receiver)
	constant Uart_SysClk_Div2:	integer	:=SystemFreq/(Uart_BPS);--Divisor of systemclock(transmitter)
end Uart_Cfg;