at91rm9200.h.svn-base

RT-Thread是发展中的下一代微内核嵌入式实时操作系统

/*
 * File      : AT91RM9200.h
 * This file is part of RT-Thread RTOS
 * COPYRIGHT (C) 2006, RT-Thread Develop Team
 *
 * The license and distribution terms for this file may be
 * found in the file LICENSE in this distribution or at
 * http://www.fayfayspace.org/license/LICENSE.
 *
 * Change Logs:
 * Date           Author       Notes
 * 2006-33-24     Bernard      first version
 */

#ifndef __AT91RM9200_H__
#define __AT91RM9200_H__

/*!
 * \file AT91RM9200.h
 * \brief AMTEL AT91RM9200 definitions
 */

#ifdef __cplusplus
extern "C" {
#endif

/*!
 * \addtogroup xgAT91RM9200
 */
/*@{*/

typedef volatile unsigned int AT91_REG;	/* Hardware register definition */

#define AT91C_TCB0_BMR	*((AT91_REG *) 0xFFFA00C4)	/* (TCB0) TC Block Mode Register */
#define AT91C_TCB0_BCR	*((AT91_REG *) 0xFFFA00C0)	/* (TCB0) TC Block Control Register */

#define AT91C_US0_CR	*((AT91_REG *) 0xFFFC0000)	/* (US0) Control Register */
#define AT91C_US0_MR	*((AT91_REG *) 0xFFFC0004)	/* (US0) Mode Register */
#define AT91C_US0_IER	*((AT91_REG *) 0xFFFC0008)	/* (US0) Interrupt Enable Register */
#define AT91C_US0_IDR	*((AT91_REG *) 0xFFFC000C)	/* (US0) Interrupt Disable Register */
#define AT91C_US0_IMR	*((AT91_REG *) 0xFFFC0010)	/* (US0) Interrupt Mask Register */
#define AT91C_US0_CSR	*((AT91_REG *) 0xFFFC0014)	/* (US0) Channel Status Register */
#define AT91C_US0_RHR	*((AT91_REG *) 0xFFFC0018)	/* (US0) Receiver Holding Register */
#define AT91C_US0_THR	*((AT91_REG *) 0xFFFC001C)	/* (US0) Transmitter Holding Register */
#define AT91C_US0_BRGR	*((AT91_REG *) 0xFFFC0020)	/* (US0) Baud Rate Generator Register */
#define AT91C_US0_RTOR	*((AT91_REG *) 0xFFFC0024)	/* (US0) Receiver Time-out Register */
#define AT91C_US0_TTGR	*((AT91_REG *) 0xFFFC0028)	/* (US0) Transmitter Time-guard Register */
#define AT91C_US0_FIDI	*((AT91_REG *) 0xFFFC0040)	/* (US0) FI_DI_Ratio Register */
#define AT91C_US0_NER	*((AT91_REG *) 0xFFFC0044)	/* (US0) Nb Errors Register */
#define AT91C_US0_XXR	*((AT91_REG *) 0xFFFC0048)	/* (US0) XON_XOFF Register */
#define AT91C_US0_IF	*((AT91_REG *) 0xFFFC004C)	/* (US0) IRDA_FILTER Register */

#define AT91C_US_RSTRX	((unsigned int) 0x1 <<  2)	/* (DBGU) Reset Receiver */
#define AT91C_US_RSTTX	((unsigned int) 0x1 <<  3)	/* (DBGU) Reset Transmitter */
#define AT91C_US_RXEN	((unsigned int) 0x1 <<  4)	/* (DBGU) Receiver Enable */
#define AT91C_US_RXDIS	((unsigned int) 0x1 <<  5)	/* (DBGU) Receiver Disable */
#define AT91C_US_TXEN	((unsigned int) 0x1 <<  6)	/* (DBGU) Transmitter Enable */
#define AT91C_US_TXDIS	((unsigned int) 0x1 <<  7)	/* (DBGU) Transmitter Disable */

#define AT91C_US_CLKS_CLOCK		((unsigned int) 0x0 <<  4) /* (USART) Clock */
#define AT91C_US_CHRL_8_BITS	((unsigned int) 0x3 <<  6) /* (USART) Character Length: 8 bits */
#define AT91C_US_PAR_NONE		((unsigned int) 0x4 <<  9) /* (DBGU) No Parity */
#define AT91C_US_NBSTOP_1_BIT	((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */

#define AT91C_SPI_CSR	*((AT91_REG *) 0xFFFE0030)	/* (SPI) Chip Select Register */
#define AT91C_PMC_PCER  *((AT91_REG *) 0xFFFFFC10)	/* (PMC) Peripheral Clock Enable Register */
#define AT91C_PIOA_PER  *((AT91_REG *) 0xFFFFF400)	/* (PIOA) PIO Enable Register */
#define AT91C_PIOA_PDR  *((AT91_REG *) 0xFFFFF404)	/* (PIOA) PIO Disable Register */
#define AT91C_PIOA_PSR  *((AT91_REG *) 0xFFFFF408)	/* (PIOA) PIO Status Register */
#define AT91C_PIOA_OER  *((AT91_REG *) 0xFFFFF410)	/* (PIOA) PIO Output Enable Register */
#define AT91C_PIOA_ODR  *((AT91_REG *) 0xFFFFF414)	/* (PIOA) PIO Output Disable Register */
#define AT91C_PIOA_OSR  *((AT91_REG *) 0xFFFFF418)	/* (PIOA) PIO Output Status Register */
#define AT91C_PIOA_IFER	*((AT91_REG *) 0xFFFFF420)	/* (PIOA) PIO Glitch Input Filter Enable Register */
#define AT91C_PIOA_IFDR	*((AT91_REG *) 0xFFFFF424)	/* (PIOA) PIO Glitch Input Filter Disable Register */
#define AT91C_PIOA_IFSR	*((AT91_REG *) 0xFFFFF428)	/* (PIOA) PIO Glitch Input Filter Status Register */
#define AT91C_PIOA_SODR	*((AT91_REG *) 0xFFFFF430)	/* (PIOA) PIO Set Output Data Register */
#define AT91C_PIOA_CODR	*((AT91_REG *) 0xFFFFF434)	/* (PIOA) PIO Clear Output Data Register */
#define AT91C_PIOA_ODSR	*((AT91_REG *) 0xFFFFF438)	/* (PIOA) PIO Output Data Status Register */
#define AT91C_PIOA_PDSR	*((AT91_REG *) 0xFFFFF43C)	/* (PIOA) PIO Pin Data Status Register */
#define AT91C_PIOA_IER	*((AT91_REG *) 0xFFFFF440)	/* (PIOA) PIO Interrupt Enable Register */
#define AT91C_PIOA_IDR  *((AT91_REG *) 0xFFFFF444)	/* (PIOA) PIO Interrupt Disable Register */
#define AT91C_PIOA_IMR  *((AT91_REG *) 0xFFFFF448)	/* (PIOA) PIO Interrupt Mask Register */
#define AT91C_PIOA_ISR  *((AT91_REG *) 0xFFFFF44C)	/* (PIOA) PIO Interrupt Status Register */
#define AT91C_PIOA_MDER	*((AT91_REG *) 0xFFFFF450)	/* (PIOA) PIO Multi-drive Enable Register */
#define AT91C_PIOA_MDDR	*((AT91_REG *) 0xFFFFF454)	/* (PIOA) PIO Multi-drive Disable Register */
#define AT91C_PIOA_MDSR	*((AT91_REG *) 0xFFFFF458)	/* (PIOA) PIO Multi-drive Status Register */
#define AT91C_PIOA_PUDR	*((AT91_REG *) 0xFFFFF460)	/* (PIOA) PIO Pull-up Disable Register */
#define AT91C_PIOA_PUER	*((AT91_REG *) 0xFFFFF464)	/* (PIOA) PIO Pull-up Enable Register */
#define AT91C_PIOA_PUSR	*((AT91_REG *) 0xFFFFF468)	/* (PIOA) PIO Pull-up Status Register */
#define AT91C_PIOA_ASR	*((AT91_REG *) 0xFFFFF470)	/* (PIOA) PIO Peripheral A Select Register */
#define AT91C_PIOA_BSR	*((AT91_REG *) 0xFFFFF474)	/* (PIOA) PIO Peripheral B Select Register */
#define AT91C_PIOA_ABSR	*((AT91_REG *) 0xFFFFF478)	/* (PIOA) PIO Peripheral AB Select Register */
#define AT91C_PIOA_OWER	*((AT91_REG *) 0xFFFFF4A0)	/* (PIOA) PIO Output Write Enable Register */
#define AT91C_PIOA_OWDR	*((AT91_REG *) 0xFFFFF4A4)	/* (PIOA) PIO Output Write Disable Register */
#define AT91C_PIOA_OWSR	*((AT91_REG *) 0xFFFFF4A8)	/* (PIOA) PIO Output Write Status Register */
#define AT91C_PIOB_PDR	*((AT91_REG *) 0xFFFFF604)	/* (PIOB) PIO Disable Register */

#define AT91C_PIO_PA30	((unsigned int) 1 << 30)	/* Pin Controlled by PA30 */
#define AT91C_PIO_PC0	((unsigned int) 1 <<  0)	/* Pin Controlled by PC0 */
#define AT91C_PC0_BFCK	AT91C_PIO_PC0				/*  Burst Flash Clock */
#define AT91C_PA30_DRXD	AT91C_PIO_PA30				/*  DBGU Debug Receive Data */
#define AT91C_PIO_PA31	((unsigned int) 1 << 31)	/* Pin Controlled by PA31 */
#define AT91C_PA25_TWD	((unsigned int) 1 << 25)
#define AT91C_PA26_TWCK	((unsigned int) 1 << 26)
#define AT91C_PA31_DTXD	AT91C_PIO_PA31				/*  DBGU Debug Transmit Data */
#define AT91C_PIO_PA17	((unsigned int) 1 << 17)	/* Pin Controlled by PA17 */
#define AT91C_PA17_TXD0	AT91C_PIO_PA17				/*  USART0 Transmit Data */
#define AT91C_PIO_PA18	((unsigned int) 1 << 18)	/* Pin Controlled by PA18 */
#define AT91C_PA18_RXD0	AT91C_PIO_PA18				/*  USART0 Receive Data */
#define AT91C_PIO_PB20	((unsigned int) 1 << 20)	/* Pin Controlled by PB20 */
#define AT91C_PB20_RXD1	AT91C_PIO_PB20				/*  USART1 Receive Data */
#define AT91C_PIO_PB21	((unsigned int) 1 << 21)	/* Pin Controlled by PB21 */
#define AT91C_PB21_TXD1	AT91C_PIO_PB21				/*  USART1 Transmit Data */

/* Timer Counter Interface */
#define AT91C_TCB_SYNC			((unsigned int) 0x1 <<  0)	/* (TCB) Synchro Command */

#define AT91C_TCB_TC0XC0S		((unsigned int) 0x1 <<  0)	/* (TCB) External Clock Signal 0 Selection */
#define AT91C_TCB_TC0XC0S_TCLK0	((unsigned int) 0x0)		/* (TCB) TCLK0 connected to XC0 */
#define AT91C_TCB_TC0XC0S_NONE	((unsigned int) 0x1)		/* (TCB) None signal connected to XC0 */
#define AT91C_TCB_TC0XC0S_TIOA1	((unsigned int) 0x2)		/* (TCB) TIOA1 connected to XC0 */
#define AT91C_TCB_TC0XC0S_TIOA2	((unsigned int) 0x3)		/* (TCB) TIOA2 connected to XC0 */

#define AT91C_TCB_TC1XC1S		((unsigned int) 0x1 << 2)	/* (TCB) External Clock Signal 1 Selection */
#define AT91C_TCB_TC1XC1S_TCLK1	((unsigned int) 0x0 << 2)	/* (TCB) TCLK1 connected to XC1 */
#define AT91C_TCB_TC1XC1S_NONE	((unsigned int) 0x1 << 2)	/* (TCB) None signal connected to XC1 */
#define AT91C_TCB_TC1XC1S_TIOA0	((unsigned int) 0x2 << 2)	/* (TCB) TIOA0 connected to XC1 */
#define AT91C_TCB_TC1XC1S_TIOA2	((unsigned int) 0x3 << 2)	/* (TCB) TIOA2 connected to XC1 */

#define AT91C_TCB_TC2XC2S		((unsigned int) 0x1 << 4)	/* (TCB) External Clock Signal 2 Selection */
#define AT91C_TCB_TC2XC2S_TCLK2	((unsigned int) 0x0 << 4)	/* (TCB) TCLK2 connected to XC2 */
#define AT91C_TCB_TC2XC2S_NONE	((unsigned int) 0x1 << 4)	/* (TCB) None signal connected to XC2 */
#define AT91C_TCB_TC2XC2S_TIOA0	((unsigned int) 0x2 << 4)	/* (TCB) TIOA0 connected to XC2 */
#define AT91C_TCB_TC2XC2S_TIOA2	((unsigned int) 0x3 << 4)	/* (TCB) TIOA2 connected to XC2 */

/* Peripheral ID Definitions */
#define AT91C_ID_SYS	(1)		/* System Peripheral */
#define AT91C_ID_PIOA	(2)		/* PIO port A */
#define AT91C_ID_PIOB	(3)		/* PIO port B */
#define AT91C_ID_PIOC	(4)		/* PIO port C */
#define AT91C_ID_USART0	(6)		/* USART 0 */
#define AT91C_ID_USART1	(7)		/* USART 1 */
#define AT91C_ID_TWI    (12)	/* Two Wire Interface */
#define AT91C_ID_SPI    (13)	/* Serial Peripheral Interface */
#define AT91C_ID_TC0    (17)	/* Timer Counter 0 */
#define AT91C_ID_EMAC   (24)	/* Ethernet MAC */

struct rt_hw_register
{
	unsigned long r0;
	unsigned long r1;
	unsigned long r2;
	unsigned long r3;
	unsigned long r4;
	unsigned long r5;
	unsigned long r6;
	unsigned long r7;
	unsigned long r8;
	unsigned long r9;
	unsigned long r10;
	unsigned long fp;
	unsigned long ip;
	unsigned long sp;
	unsigned long lr;
	unsigned long pc;
	unsigned long cpsr;
	unsigned long ORIG_r0;
};

/*@}*/

#ifdef __cplusplus
}
#endif

#endif