cpu.c

RT-Thread是发展中的下一代微内核嵌入式实时操作系统

/*
 * File      : cpu.c
 * This file is part of RT-Thread RTOS
 * COPYRIGHT (C) 2006, RT-Thread Develop Team
 *
 * The license and distribution terms for this file may be
 * found in the file LICENSE in this distribution or at
 * http://www.fayfayspace.org/license/LICENSE.
 *
 * Change Logs:
 * Date           Author       Notes
 * 2006-02-24     Bernard      first version
 */

#include <rtthread.h>

/*!
 * \addtogroup xgAT91RM9200
 */
/*@{*/

/* read co-processor 15, register #1 (control register) */
static rt_base read_p15_c1(void)
{
    unsigned long value;

    __asm__ __volatile__(
	"mrc     p15, 0, %0, c1, c0, 0   @ read control reg\n"
	: "=r" (value)
	:
	: "memory");

    /* rt_kprintf("p15/c1 is = %08lx\n", value); */
    return value;
}

/* write to co-processor 15, register #1 (control register) */
static void write_p15_c1(rt_base value)
{
    /* rt_kprintf("write %08lx to p15/c1\n", value); */

    __asm__ __volatile__(
	"mcr     p15, 0, %0, c1, c0, 0   @ write it back\n"
	: "=r" (value)
	:
	: "memory");

    read_p15_c1();
}

static void cp_delay(void)
{
    volatile int i;

    /* copro seems to need some delay between reading and writing */
    for (i=0; i<100; i++);
}

#define C1_MMU				(1<<0)		/* mmu off/on */
#define C1_ALIGN			(1<<1)		/* alignment faults off/on */
#define C1_IDC				(1<<2)		/* icache and/or dcache off/on */
#define C1_WRITE_BUFFER		(1<<3)		/* write buffer off/on */
#define C1_BIG_ENDIAN		(1<<7)		/* big endian off/on */
#define C1_SYS_PROT			(1<<8)		/* system protection */
#define C1_ROM_PROT			(1<<9)		/* ROM protection */
#define C1_HIGH_VECTORS		(1<<13)		/* location of vectors: low/high addresses */

/*!
 * \brief enable I-Cache of cpu
 *
 * this function will enable I-Cache of CPU
 *
 */
void rt_hw_cpu_icache_enable()
{
    rt_base reg;
    reg = read_p15_c1();
    cp_delay();
    write_p15_c1(reg | C1_IDC);
}

/*!
 * \brief disable I-Cache of cpu
 *
 * this function will disable I-Cache of CPU
 *
 */
void rt_hw_cpu_icache_disable()
{
    rt_base reg;
    reg = read_p15_c1();
    cp_delay();
    write_p15_c1(reg & ~C1_IDC);
}

/*!
 * \brief get the status of I-Cache
 *
 * this function will get the status of I-Cache
 *
 */
int rt_hw_cpu_icache_status()
{
    return (read_p15_c1() & C1_IDC) != 0;
}

/*!
 * \brief enable D-Cache of cpu
 *
 * this function will enable D-Cache of CPU
 *
 */
void rt_hw_cpu_dcache_enable()
{
    rt_base reg;
    reg = read_p15_c1();
    cp_delay();
    write_p15_c1(reg | C1_IDC);
}

/*!
 * \brief disable D-Cache of cpu
 *
 * this function will disable D-Cache of CPU
 *
 */
void rt_hw_cpu_dcache_disable()
{
    rt_base reg;
    reg = read_p15_c1();
    cp_delay();
    write_p15_c1(reg & ~C1_IDC);
}

/*!
 * \brief get the status of D-Cache
 *
 * this function will get the status of D-Cache
 *
 */
int rt_hw_cpu_dcache_status()
{
    return (read_p15_c1() & C1_IDC) != 0;
}

/*!
 * \brief reset CPU
 *
 * this function will reset CPU
 *
 */
void rt_hw_cpu_reset()
{
}

/*!
 * \brief shutdown CPU
 *
 * this function will shutdown CPU
 *
 */
void rt_hw_cpu_shutdown()
{
	rt_kprintf("shutdown...\n");

	while (1);
}

/*@}*/