start.s

RT-Thread是发展中的下一代微内核嵌入式实时操作系统

/*
 * File      : start.S
 * This file is part of RT-Thread RTOS
 * COPYRIGHT (C) 2006, RT-Thread Development Team
 *
 * The license and distribution terms for this file may be
 * found in the file LICENSE in this distribution or at
 * http://openlab.rt-thread.com/license/LICENSE
 *
 * Change Logs:
 * Date           Author       Notes
 * 2006-03-13     Bernard      first version
 * 2006-10-05     Alsor.Z      for s3c2410 initialize
 */

/**
 * @addtogroup S3C2410
 */
/*@{*/

#define CONFIG_STACKSIZE 8192

	.equ USERMODE, 	0x10
	.equ FIQMODE,	0x11
	.equ IRQMODE,	0x12
	.equ SVCMODE,	0x13
	.equ ABORTMODE,	0x17
	.equ UNDEFMODE,	0x1b
	.equ MODEMASK,	0x1f
	.equ NOINT,		0xc0

.section .init, "ax"
.code 32
.globl _start
_start:
	b	reset
	ldr	pc, _vector_undef
	ldr	pc, _vector_swi
	ldr	pc, _vector_pabt
	ldr	pc, _vector_dabt
	ldr	pc, _vector_resv
	ldr	pc, _vector_irq
	ldr	pc, _vector_fiq

_vector_undef:	.word vector_undef
_vector_swi:	.word vector_swi
_vector_pabt:	.word vector_pabt
_vector_dabt:	.word vector_dabt
_vector_resv:	.word vector_resv
_vector_irq:	.word vector_irq
_vector_fiq:	.word vector_fiq

	.balignl 16,0xdeadbeef

_TEXT_BASE:
	.word	TEXT_BASE

/*
 * rtthread kernel start and end
 * which are defined in linker script
 */
.globl _rtthread_start
_rtthread_start:.word _start
.globl _rtthread_end
_rtthread_end:	.word  _end

/*
 * rtthread bss start and end
 * which are defined in linker script
 */
.globl _bss_start
_bss_start:	.word __bss_start
.globl _bss_end
_bss_end:	.word __bss_end

/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:.word _irq_stack_start + 1024
.globl FIQ_STACK_START
FIQ_STACK_START:.word _fiq_stack_start + 1024
.globl UNDEFINED_STACK_START
UNDEFINED_STACK_START:.word _undefined_stack_start + 512
.globl ABORT_STACK_START
ABORT_STACK_START:.word _abort_stack_start + 512

	.equ RAM_BASE,	0x00000000	//Start address of RAM
	.equ ROM_BASE,	0x30000000	//Start address of Flash

	.equ INTMSK,	0x4a000008
	.equ WTCON, 	0x53000000
	.equ INTSUBMSK, 0x4a00001c
	.equ LOCKTIME,	0x4c000000

	.equ MPLLCON,	0x4c000004
	.equ M_MDIV,	0x20
	.equ M_PDIV,	0x4
	.equ M_SDIV,	0x2
	.equ CLKDIVN,	0x4c000014	//Clock divider control
	.equ GPHCON,	0x56000070	//Port H control
	.equ GPHUP,		0x56000078	//Pull-up control H
	.equ BWSCON,	0x48000000	//Bus width & wait status
	.equ BANKCON0,	0x48000004	//Boot ROM control
	.equ BANKCON1,	0x48000008	//BANK1 control
	.equ BANKCON2,	0x4800000c	//BANK2 cControl
	.equ BANKCON3,	0x48000010	//BANK3 control
	.equ BANKCON4,	0x48000014	//BANK4 control
	.equ BANKCON5,	0x48000018	//BANK5 control
	.equ BANKCON6,	0x4800001c	//BANK6 control
	.equ BANKCON7,	0x48000020	//BANK7 control
	.equ REFRESH,	0x48000024	//DRAM/SDRAM efresh
	.equ BANKSIZE,	0x48000028	//Flexible Bank Size
	.equ MRSRB6,	0x4800002c	//Mode egister set for SDRAM
	.equ MRSRB7,	0x48000030	//Mode egister set for SDRAM

/* -----------------entry--------------- */
reset:
	/* watch dog disable */
	ldr r0,=WTCON
	ldr r1,=0x0
	str r1,[r0]

	/* set the cpu to SVC32 mode */
	mrs	r0,cpsr
	bic	r0,r0,#MODEMASK
	orr	r0,r0,#SVCMODE
	msr	cpsr,r0

	/* mask all IRQs by clearing all bits in the INTMRs */
	ldr	r1, =INTMSK
	ldr	r0, =0xffffffff
	str	r0, [r1]

	/* all sub interrupt disable */
	ldr	r1, =INTSUBMSK
	ldr	r0, =0x7ff
	str	r0, [r1]

	/* Clock divider control */
	ldr r0, =CLKDIVN
	ldr r1, =0x3
	str r1,[r0]

	/* Configure MPLL, Fin=12MHz,Fout=50MHz, 0x0005c042 or 0x000A1031*/
	ldr r0,=MPLLCON
	ldr r1, =0x0005c042
	str r1,[r0]

	/* port H control*/
	ldr r0, =GPHCON
	ldr r1, =0x280000
	str r1, [r0]

	/* pull up port H */
	ldr r0, =GPHUP
	ldr r1, =0x0
	str r1, [r0]

	ldr r0, =BWSCON
	ldr r1, =0x22111110
	str r1, [r0]

	/* Bank 0 , boot rom control */
	ldr r0, =BANKCON0
	ldr r1, =0x700
	str r1, [r0]

	/* Bank 1 control */
	ldr r0, =BANKCON1
	ldr r1, =0x700
	str r1, [r0]

	/* Bank 2 control */
	ldr r0, =BANKCON2
	ldr r1, =0x700
	str r1, [r0]

	/* Bank 3 control */
	ldr r0, =BANKCON3
	ldr r1, =0x700
	str r1, [r0]

	/* Bank 4 control */
	ldr r0, =BANKCON4
	ldr r1, =0x700
	str r1, [r0]

	/* Bank 5 control */
	ldr r0, =BANKCON5
	ldr r1, =0x700
	str r1, [r0]

	/* Bank 6 control */
	ldr r0, =BANKCON6
	ldr r1, =0x18005
	str r1, [r0]

	/* Bank 7 control */
	ldr r0, =BANKCON7
	ldr r1, =0x700
	str r1, [r0]

	/* DRAM/SDRAM refresh */
	ldr r0, =REFRESH
	ldr r1, =0x8e0459
	str r1, [r0]

	/* Flexible Bank Size */
	ldr r0, =BANKSIZE
	ldr r1, =0xB2
	str r1, [r0]

	/* Mode register set for SDRAM */
	ldr r0, =MRSRB6
	ldr r1, =0x30
	str r1, [r0]

	/* Mode register set for SDRAM */
	ldr r0, =MRSRB7
	ldr r1, =0x30
	str r1, [r0]

	/* To reduce PLL lock time, adjust the LOCKTIME register. */
	ldr r0,=LOCKTIME
	ldr r1,=0xffffff
	str r1,[r0]

	/* I Cache Enable */
/*
	mrc  p15,0,r0,c1,c0,0
	orr  r0,r0,#(1<<12)
	mcr  p15,0,r0,c1,c0,0
*/
	/* D Cache Enable */
/*
	mrc  p15,0,r0,c1,c0,0
	orr  r0,r0,#(1<<2)
	mcr  p15,0,r0,c1,c0,0
*/
	/* Align Fault Enable */
/*
	mrc  p15,0,r0,c1,c0,0
	orr  r0,r0,#(1<<1)
	mcr  p15,0,r0,c1,c0,0
*/
	/* MMU enable */
	/*
	* mrc  p15,0,r0,c1,c0,0
	* orr  r0,r0,#1
	* mcr  p15,0,r0,c1,c0,0
	*/

	/* set interrupt vector 	*/
#if defined(__FLASH_BUILD__)
	ldr	r0, ROM_BASE + _TEXT_BASE	/* source address 0x8000	*/
#else
	ldr	r0, RAM_BASE + _TEXT_BASE	/* source address 0x8000	*/
#endif
	mov	r1, #0x0			/* target address    		*/
	add	r2, r0, #0x20			/* size, 32bytes         	*/

copy_loop:
	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
	cmp	r0, r2				/* until source end addreee [r2]    */
	ble	copy_loop

	/* setup stack */
	bl	stack_setup

	/* start RT-Thread Kernel */
	ldr	pc, _rtthread_startup

_rtthread_startup: .word rtthread_startup

/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 */
	.macro	bad_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}		@ Calling r0-r12
	add     r8, sp, #S_PC

	ldr	r2, _rtthread_end
	add	r2, r2, #CONFIG_STACKSIZE
	sub	r2, r2, #8
	ldmia	r2, {r2 - r4}		@ get pc, cpsr, old_r0
	add	r0, sp, #S_FRAME_SIZE	@ restore sp_SVC

	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r4}		@ save sp_SVC, lr_SVC, pc, cpsr, old_r
	mov	r0, sp
	.endm

	.macro	get_bad_stack
	ldr	r13, _rtthread_end		@ setup our mode stack
	add	r13, r13, #CONFIG_STACKSIZE	@ resides at top of normal stack
	sub	r13, r13, #8

	str	lr, [r13]				@ save caller lr / spsr
	mrs	lr, spsr
	str     lr, [r13, #4]

	mov	r13, #SVCMODE			@ prepare SVC-Mode
	msr	spsr_c, r13
	mov	lr, pc
	movs	pc, lr
	.endm

/* exception handlers */
	.align  5
vector_undef:
	get_bad_stack
	bad_save_user_regs
	bl	rt_hw_trap_udef

	.align	5
vector_swi:
	get_bad_stack
	bad_save_user_regs
	bl 	rt_hw_trap_swi

	.align	5
vector_pabt:
	get_bad_stack
	bad_save_user_regs
	bl 	rt_hw_trap_pabt

	.align	5
vector_dabt:
	get_bad_stack
	bad_save_user_regs
	bl 	rt_hw_trap_dabt

	.align	5
vector_resv:
	get_bad_stack
	bad_save_user_regs
	bl 	rt_hw_trap_resv

.globl rt_interrupt_enter
.globl rt_interrupt_leave
.globl rt_thread_switch_interrput_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
vector_irq:
	stmfd	sp!, {r0-r12,lr}
	bl	rt_interrupt_enter
	bl	rt_hw_trap_irq
	bl	rt_interrupt_leave

	/* if rt_thread_switch_interrput_flag set, jump to _interrupt_thread_switch and don't return */
	ldr	r0, =rt_thread_switch_interrput_flag
	ldr	r1, [r0]
	cmp	r1, #1
	beq	_interrupt_thread_switch

	ldmfd	sp!, {r0-r12,lr}
	subs	pc, lr, #4

	.align	5
vector_fiq:
	stmfd	sp!,{r0-r7,lr}
	bl 	rt_hw_trap_fiq
	ldmfd	sp!,{r0-r7,lr}
	subs	pc,lr,#4

_interrupt_thread_switch:
	mov	r1,  #0				@ clear rt_thread_switch_interrput_flag
	str	r1,  [r0]

	ldmfd	sp!, {r0-r12,lr}@ reload saved registers
	stmfd	sp!, {r0-r3}	@ save r0-r3
	mov	r1,  sp
	add	sp,  sp, #16		@ restore sp
	sub	r2,  lr, #4			@ save old task's pc to r2

	mrs	r3,  spsr			@ disable interrupt
	orr	r0,  r3, #NOINT
	msr	spsr_c, r0

	ldr	r0,  =.+8			@ switch to interrupted task's stack
	movs	pc,  r0

	stmfd	sp!, {r2}		@ push old task's pc
	stmfd	sp!, {r4-r12,lr}@ push old task's lr,r12-r4
	mov	r4,  r1				@ Special optimised code below
	mov	r5,  r3
	ldmfd	r4!, {r0-r3}
	stmfd	sp!, {r0-r3}	@ push old task's r3-r0
	stmfd	sp!, {r5}		@ push old task's psr
	mrs	r4,  spsr
	stmfd	sp!, {r4}		@ push old task's spsr

	ldr	r4,  =rt_interrupt_from_thread
	ldr	r5,  [r4]
	str	sp,  [r5]			@ store sp in preempted tasks's TCB

	ldr	r6,  =rt_interrupt_to_thread
	ldr	r6,  [r6]
	ldr	sp,  [r6]			@ get new task's stack pointer

	ldmfd	sp!, {r4}		@ pop new task's spsr
	msr	SPSR_cxsf, r4
	ldmfd	sp!, {r4}		@ pop new task's psr
	msr	CPSR_cxsf, r4

	ldmfd	sp!, {r0-r12,lr,pc}	@ pop new task's r0-r12,lr & pc

stack_setup:
	mrs	r0, cpsr
	bic	r0, r0, #MODEMASK
	orr	r1, r0, #UNDEFMODE|NOINT
	msr	cpsr_cxsf, r1		@ undef mode
	ldr	sp, UNDEFINED_STACK_START

	orr	r1,r0,#ABORTMODE|NOINT
	msr	cpsr_cxsf,r1		@ abort mode
	ldr	sp, ABORT_STACK_START

	orr	r1,r0,#IRQMODE|NOINT
	msr	cpsr_cxsf,r1		@ IRQ mode
	ldr	sp, IRQ_STACK_START

	orr	r1,r0,#FIQMODE|NOINT
	msr	cpsr_cxsf,r1		@ FIQ mode
	ldr	sp, FIQ_STACK_START

	bic	r0,r0,#MODEMASK
	orr	r1,r0,#SVCMODE|NOINT
	msr	cpsr_cxsf,r1		@ SVC mode

	ldr	r0, _rtthread_end
	add	sp, r0, #CONFIG_STACKSIZE

	/* USER mode is not initialized. */

	mov	pc,lr				@ The LR register may be not valid for the mode changes.

/*@}*/