📄 pxa270.h
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/*
* File : pxa270.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-10-24 Bernard the first version
*/
/*
* The Intel PXA270 Processor, a XScale based integrated CPU
*/
#ifndef __PXA270_H__
#define __PXA270_H__
/*
* Chip select domains
*/
#define PXA2X0_CS0_START 0x00000000
#define PXA2X0_CS1_START 0x04000000
#define PXA2X0_CS2_START 0x08000000
#define PXA2X0_CS3_START 0x0c000000
#define PXA2X0_CS4_START 0x10000000
#define PXA2X0_CS5_START 0x14000000
#define PXA2X0_PCMCIA_SLOT0 0x20000000
#define PXA2X0_PCMCIA_SLOT1 0x30000000
#define PXA2X0_PERIPH_START 0x40000000
#define PXA2X0_PERIPH_END 0x480fffff
#define PXA2X0_SDRAM0_START 0xa0000000
#define PXA2X0_SDRAM1_START 0xa4000000
#define PXA2X0_SDRAM2_START 0xa8000000
#define PXA2X0_SDRAM3_START 0xac000000
#define PXA2X0_SDRAM_BANKS 4
#define PXA2X0_SDRAM_BANK_SIZE 0x04000000
/*
* Physical address of integrated peripherals
*/
#define PXA2X0_DMAC_BASE 0x40000000 /* DMA Controller */
#define PXA2X0_FFUART_BASE 0x40100000 /* Full Function UART */
#define PXA2X0_BTUART_BASE 0x40200000 /* Bluetooth UART */
#define PXA2X0_I2C_BASE 0x40300000 /* I2C Bus Interface Unit */
#define PXA2X0_I2S_BASE 0x40400000 /* Inter-IC Sound Controller */
#define PXA2X0_AC97_BASE 0x40500000 /* AC '97 Controller */
#define PXA2X0_USBDC_BASE 0x40600000 /* USB Client Controller */
#define PXA2X0_STUART_BASE 0x40700000 /* Standard UART */
#define PXA2X0_ICP_BASE 0x40800000
#define PXA2X0_RTC_BASE 0x40900000
#define PXA2X0_PWM0_BASE 0x40b00000
#define PXA2X0_PWM1_BASE 0x40c00000
#define PXA2X0_POWMAN_BASE 0x40f00000 /* Power management */
#define PXA2X0_SSP_BASE 0x41000000 /* SSP serial port */
#define PXA2X0_SSP1_BASE 0x41700000 /* PXA270 */
#define PXA2X0_SSP2_BASE 0x41900000 /* PXA270 */
#define PXA2X0_MMC_BASE 0x41100000 /* MultiMediaCard */
#define PXA2X0_CLKMAN_BASE 0x41300000 /* Clock Manager */
#define PXA2X0_MEMCTL_BASE 0x48000000 /* Memory Controller */
#define PXA2X0_USBHC_BASE 0x4c000000 /* USB Host Controller */
/* Interrupt Controller */
#define PXA2X0_INTCTL_BASE 0x40d00000
#define PXA2X0_INTCTL_ICIP (*(volatile unsigned int*)(PXA2X0_INTCTL_BASE + 0x00))
#define PXA2X0_INTCTL_ICMR (*(volatile unsigned int*)(PXA2X0_INTCTL_BASE + 0x04))
#define PXA2X0_INTCTL_ICLR (*(volatile unsigned int*)(PXA2X0_INTCTL_BASE + 0x08))
#define PXA2X0_INTCTL_ICFP (*(volatile unsigned int*)(PXA2X0_INTCTL_BASE + 0x0c))
#define PXA2X0_INTCTL_ICPR (*(volatile unsigned int*)(PXA2X0_INTCTL_BASE + 0x10))
#define PXA2X0_INTCTL_ICCR (*(volatile unsigned int*)(PXA2X0_INTCTL_BASE + 0x14))
/* DMAC */
#define DMAC_N_CHANNELS 16
#define DMAC_N_CHANNELS_PXA27X 32
#define DMAC_N_PRIORITIES 3
#define DMAC_N_PRIORITIES_PXA27X 4
#define DMAC_DCSR(n) ((n)*4)
#define DMAC_DINT 0x00f0 /* DMA interrupt */
#define DMAC_DRCMR(n) (0x100+(n)*4) /* Channel map register */
#define DMAC_DDADR(n) (0x0200+(n)*16)
#define DMAC_DSADR(n) (0x0204+(n)*16)
#define DMAC_DTADR(n) (0x0208+(n)*16)
#define DMAC_DCMD(n) (0x020c+(n)*16)
/* Power Manager */
#define POWMAN_PMCR 0x00
#define POWMAN_PSSR 0x04 /* Sleep Status register */
#define POWMAN_PSPR 0x08
#define POWMAN_PWER 0x0c
#define POWMAN_PRER 0x10
#define POWMAN_PFER 0x14
#define POWMAN_PEDR 0x18
#define POWMAN_PCFR 0x1c /* General Configuration register */
#define POWMAN_PGSR0 0x20 /* GPIO Sleep State register */
#define POWMAN_PGSR1 0x24
#define POWMAN_PGSR2 0x28
#define POWMAN_PGSR3 0x2c /* PXA270 */
#define POWMAN_RCSR 0x30 /* Reset Controller Status register */
#define POWMAN_PSLR 0x34 /* PXA270 */
#define POWMAN_PKWR 0x50 /* PXA270 */
#define POWMAN_PKSR 0x54 /* PXA270 */
/* Power Manager I2C unit */
#define POWMAN_PIDBR 0x188
#define POWMAN_PICR 0x190
#define POWMAN_PISR 0x198
#define POWMAN_PISAR 0x1a0
/* Clock Manager */
#define CLKMAN_CCCR 0x00 /* Core Clock Configuration */
#define CLKMAN_CKEN 0x04 /* Clock Enable Register */
#define CLKMAN_OSCC 0x08 /* Oscillator Configuration Register */
/*
* RTC
*/
#define RTC_RCNR 0x0000 /* count register */
#define RTC_RTAR 0x0004 /* alarm register */
#define RTC_RTSR 0x0008 /* status register */
#define RTC_RTTR 0x000c /* trim register */
/*
* Memory Controller
*/
#define MEMCTL_MDCNFG 0x00
#define MEMCTL_MDREFR 0x04 /* refresh control register */
#define MEMCTL_MSC0 0x08 /* Asynchronous Static memory Control CS[01] */
#define MEMCTL_MSC1 0x0c /* Asynchronous Static memory Control CS[23] */
#define MEMCTL_MSC2 0x10 /* Asynchronous Static memory Control CS[45] */
#define MEMCTL_MECR 0x14 /* Expansion memory configuration */
#define MEMCTL_MDMRS 0x40
#define MEMCTL_ARB_CNTRL 0x48 /* System Bus Arbiter */
/* OS Timer */
#define PXA2X0_OST_BASE 0x40a00000
#define PXA2X0_OST_OSMR0 (*(volatile unsigned int*)(PXA2X0_OST_BASE + 0x0000)) /* Match 0 */
#define PXA2X0_OST_OSMR1 (*(volatile unsigned int*)(PXA2X0_OST_BASE + 0x0004)) /* Match 1 */
#define PXA2X0_OST_OSMR2 (*(volatile unsigned int*)(PXA2X0_OST_BASE + 0x0008)) /* Match 2 */
#define PXA2X0_OST_OSMR3 (*(volatile unsigned int*)(PXA2X0_OST_BASE + 0x000c)) /* Match 3 */
#define PXA2X0_OST_OSCR0 (*(volatile unsigned int*)(PXA2X0_OST_BASE + 0x0010)) /* Counter 0 */
#define PXA2X0_OST_OSCR4 (*(volatile unsigned int*)(PXA2X0_OST_BASE + 0x0040)) /* Counter 4 */
#define PXA2X0_OST_OMCR4 (*(volatile unsigned int*)(PXA2X0_OST_BASE + 0x00c0)) /* Counter 4 match control */
#define PXA2X0_OST_OSMR4 (*(volatile unsigned int*)(PXA2X0_OST_BASE + 0x0080)) /* Counter 4 match */
#define PXA2X0_OST_OSCR5 (*(volatile unsigned int*)(PXA2X0_OST_BASE + 0x0044)) /* Counter 5 */
#define PXA2X0_OST_OMCR5 (*(volatile unsigned int*)(PXA2X0_OST_BASE + 0x00c4)) /* Counter 5 match control */
#define PXA2X0_OST_OSMR5 (*(volatile unsigned int*)(PXA2X0_OST_BASE + 0x0084)) /* Counter 4 match */
#define PXA2X0_OST_OSSR (*(volatile unsigned int*)(PXA2X0_OST_BASE + 0x0014)) /* Status (all counters) */
#define PXA2X0_OST_OWER (*(volatile unsigned int*)(PXA2X0_OST_BASE + 0x0018)) /* Watchdog Enable */
#define PXA2X0_OST_OIER (*(volatile unsigned int*)(PXA2X0_OST_BASE + 0x001c)) /* Interrupt Enable */
/* GPIO Unit */
#define PXA2X0_GPIO_BASE 0x40e00000
#define PXA2X0_GPIO_GPLR0 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x00)) /* Level reg [31:0] */
#define PXA2X0_GPIO_GPLR1 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x04)) /* Level reg [63:32] */
#define PXA2X0_GPIO_GPLR2 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x08)) /* Level reg [80:64] PXA 270 [95:64] */
#define PXA2X0_GPIO_GPDR0 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x0c)) /* dir reg [31:0] */
#define PXA2X0_GPIO_GPDR1 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x10)) /* dir reg [63:32] */
#define PXA2X0_GPIO_GPDR2 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x14)) /* dir reg [80:64] PXA 270 [95:64] */
#define PXA2X0_GPIO_GPSR0 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x18)) /* set reg [31:0] */
#define PXA2X0_GPIO_GPSR1 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x1c)) /* set reg [63:32] */
#define PXA2X0_GPIO_GPSR2 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x20)) /* set reg [80:64] PXA 270 [95:64] */
#define PXA2X0_GPIO_GPCR0 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x24)) /* clear reg [31:0] */
#define PXA2X0_GPIO_GPCR1 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x28)) /* clear reg [63:32] */
#define PXA2X0_GPIO_GPCR2 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x2c)) /* clear reg [80:64] PXA 270 [95:64] */
#define PXA2X0_GPIO_GPER0 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x30)) /* rising edge [31:0] */
#define PXA2X0_GPIO_GPER1 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x34)) /* rising edge [63:32] */
#define PXA2X0_GPIO_GPER2 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x38)) /* rising edge [80:64] PXA 270 [95:64] */
#define PXA2X0_GPIO_GRER0 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x30)) /* rising edge [31:0] */
#define PXA2X0_GPIO_GRER1 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x34)) /* rising edge [63:32] */
#define PXA2X0_GPIO_GRER2 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x38)) /* rising edge [80:64] PXA 270 [95:64] */
#define PXA2X0_GPIO_GFER0 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x3c)) /* falling edge [31:0] */
#define PXA2X0_GPIO_GFER1 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x40)) /* falling edge [63:32] */
#define PXA2X0_GPIO_GFER2 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x44)) /* falling edge [80:64] PXA 270 [95:64] */
#define PXA2X0_GPIO_GEDR0 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x48)) /* edge detect [31:0] */
#define PXA2X0_GPIO_GEDR1 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x4c)) /* edge detect [63:32] */
#define PXA2X0_GPIO_GEDR2 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x50)) /* edge detect [80:64] PXA 270 [95:64] */
#define PXA2X0_GPIO_GAFR0_L (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x54)) /* alternate function [15:0] */
#define PXA2X0_GPIO_GAFR0_U (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x58)) /* alternate function [31:16] */
#define PXA2X0_GPIO_GAFR1_L (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x5c)) /* alternate function [47:32] */
#define PXA2X0_GPIO_GAFR1_U (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x60)) /* alternate function [63:48] */
#define PXA2X0_GPIO_GAFR2_L (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x64)) /* alternate function [79:64] */
#define PXA2X0_GPIO_GAFR2_U (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x68)) /* alternate function [80] PXA 270 [95:80] */
#define PXA2X0_GPIO_GAFR3_L (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x6C)) /* alternate function PXA 270 [111:96] */
#define PXA2X0_GPIO_GAFR3_U (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x70)) /* alternate function PXA 270 [120:112] */
#define PXA2X0_GPIO_GPLR3 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x100)) /* Level PXA 270 [120:96] */
#define PXA2X0_GPIO_GPDR3 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x10C)) /* dir reg PXA 270 [120:96] */
#define PXA2X0_GPIO_GPSR3 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x118)) /* set reg PXA 270 [120:96] */
#define PXA2X0_GPIO_GPCR3 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x124)) /* clear reg PXA 270 [120:96] */
#define PXA2X0_GPIO_GRER3 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x130)) /* rising edge PXA 270 [120:96] */
#define PXA2X0_GPIO_GFER3 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x13c)) /* falling edge PXA 270 [120:96] */
#define PXA2X0_GPIO_GEDR3 (*(volatile unsigned int*)(PXA2X0_GPIO_BASE + 0x148)) /* edge detect PXA270 [120:96] */
/*
* LCD Controller
*/
#define PXA2X0_LCDC_BASE 0x44000000
#define PXA2X0_LCDC_LCCR0 (*(volatile unsigned int*)(PXA2X0_LCDC_BASE + 0x000)) /* Controller Control Register 0 */
#define PXA2X0_LCDC_LCCR1 (*(volatile unsigned int*)(PXA2X0_LCDC_BASE + 0x004)) /* Controller Control Register 1 */
#define PXA2X0_LCDC_LCCR2 (*(volatile unsigned int*)(PXA2X0_LCDC_BASE + 0x008)) /* Controller Control Register 2 */
#define PXA2X0_LCDC_LCCR3 (*(volatile unsigned int*)(PXA2X0_LCDC_BASE + 0x00c)) /* Controller Control Register 2 */
#define PXA2X0_LCDC_FBR0 (*(volatile unsigned int*)(PXA2X0_LCDC_BASE + 0x020)) /* DMA ch0 frame branch register */
#define PXA2X0_LCDC_FBR1 (*(volatile unsigned int*)(PXA2X0_LCDC_BASE + 0x024)) /* DMA ch1 frame branch register */
#define PXA2X0_LCDC_LCSR (*(volatile unsigned int*)(PXA2X0_LCDC_BASE + 0x038)) /* controller status register */
#define PXA2X0_LCDC_LIIDR (*(volatile unsigned int*)(PXA2X0_LCDC_BASE + 0x03c)) /* controller interrupt ID Register */
#define PXA2X0_LCDC_TRGBR (*(volatile unsigned int*)(PXA2X0_LCDC_BASE + 0x040)) /* TMED RGB Speed Register */
#define PXA2X0_LCDC_TCR (*(volatile unsigned int*)(PXA2X0_LCDC_BASE + 0x044)) /* TMED Control Register */
#define PXA2X0_LCDC_FDADR0 (*(volatile unsigned int*)(PXA2X0_LCDC_BASE + 0x200)) /* DMA ch0 frame descriptor address */
#define PXA2X0_LCDC_FSADR0 (*(volatile unsigned int*)(PXA2X0_LCDC_BASE + 0x204)) /* DMA ch0 frame source address */
#define PXA2X0_LCDC_FIDR0 (*(volatile unsigned int*)(PXA2X0_LCDC_BASE + 0x208)) /* DMA ch0 frame ID register */
#define PXA2X0_LCDC_LDCMD0 (*(volatile unsigned int*)(PXA2X0_LCDC_BASE + 0x20c)) /* DMA ch0 command register */
#define PXA2X0_LCDC_FDADR1 (*(volatile unsigned int*)(PXA2X0_LCDC_BASE + 0x210)) /* DMA ch1 frame descriptor address */
#define PXA2X0_LCDC_FSADR1 (*(volatile unsigned int*)(PXA2X0_LCDC_BASE + 0x214)) /* DMA ch1 frame source address */
#define PXA2X0_LCDC_FIDR1 (*(volatile unsigned int*)(PXA2X0_LCDC_BASE + 0x218)) /* DMA ch1 frame ID register */
#define PXA2X0_LCDC_LDCMD1 (*(volatile unsigned int*)(PXA2X0_LCDC_BASE + 0x21c)) /* DMA ch1 command register */
/*
* [0..1,15..16] are used as soft intrs by SI_TO_IRQBIT,
* and [4..6] are not likely to be used by us.
*/
#define PXA2X0_INT_USBH2 2 /* USB host (all other events) */
#define PXA2X0_INT_USBH1 3 /* USB host (OHCI) */
#define PXA2X0_INT_OST 7 /* OS timers */
#define PXA2X0_INT_GPIO0 8
#define PXA2X0_INT_GPIO1 9
#define PXA2X0_INT_GPION 10 /* IRQ from GPIO[2..80] */
#define PXA2X0_INT_USB 11
#define PXA2X0_INT_PMU 12
#define PXA2X0_INT_I2S 13
#define PXA2X0_INT_AC97 14
#define PXA2X0_INT_LCD 17
#define PXA2X0_INT_I2C 18
#define PXA2X0_INT_ICP 19
#define PXA2X0_INT_STUART 20
#define PXA2X0_INT_BTUART 21
#define PXA2X0_INT_FFUART 22
#define PXA2X0_INT_MMC 23
#define PXA2X0_INT_SSP 24
#define PXA2X0_INT_DMA 25
#define PXA2X0_INT_OST0 26
#define PXA2X0_INT_OST1 27
#define PXA2X0_INT_OST2 28
#define PXA2X0_INT_OST3 29
#define PXA2X0_INT_RTCHZ 30
#define PXA2X0_INT_ALARM 31 /* RTC Alarm interrupt */
#endif
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