📄 cpu.c.svn-base
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/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE.
*
* Change Logs:
* Date Author Notes
* 2006-10-24 Bernard first version
*/
#include <rtthread.h>
#include "pxa270.h"
/**
* @addtogroup PXA270
*/
/*@{*/
/**
* this function will enable I-Cache of CPU
*/
void rt_hw_cpu_icache_enable()
{
register rt_uint32 i; /* read control register */ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); /* set i-cache */ i |= 0x1000; /* write back to control register */ asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));}
/**
* @brief disable I-Cache of cpu
*
* this function will disable I-Cache of CPU
*
*/
void rt_hw_cpu_icache_disable()
{
register rt_uint32 i; /* read control register */ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); /* clear i-cache */ i &= ~0x1000; /* write back to control register */ asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); /* flush i-cache */ asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));}
/**
* @brief get the status of I-Cache
*
* this function will get the status of I-Cache
*
*/
int rt_hw_cpu_icache_status()
{
register rt_uint32 i; /* read control register */ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); /* return bit */ return (i & 0x1000);}
/**
* @brief enable D-Cache of cpu
*
* this function will enable D-Cache of CPU
*
*/
void rt_hw_cpu_dcache_enable(void)
{
return;
}
/**
* @brief disable D-Cache of cpu
*
* this function will disable D-Cache of CPU
*
*/
void rt_hw_cpu_dcache_disable(void)
{
return;
}
/**
* @brief get the status of D-Cache
*
* this function will get the status of D-Cache
*
*/
int rt_hw_cpu_dcache_status(void)
{
return 0;
}
/**
* @brief reset CPU
*
* this function will reset CPU
*
*/
void rt_hw_cpu_reset()
{
}
/**
* @brief shutdown CPU
*
* this function will shutdown CPU
*
*/
void rt_hw_cpu_shutdown()
{
rt_kprintf("shutdown...\n");
while (1);
}
/*@}*/
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