lowlevel.s.svn-base

RT-Thread是发展中的下一代微内核嵌入式实时操作系统

/*
 * File      : lowlevel.S
 * This file is part of RT-Thread RTOS
 * COPYRIGHT (C) 2006, RT-Thread Develop Team
 *
 * The license and distribution terms for this file may be
 * found in the file LICENSE in this distribution or at
 * http://openlab.rt-thread.com/license/LICENSE
 *
 * Change Logs:
 * Date           Author       Notes
 * 2006-10-26     Bernard      the first version
 */

#define	CPWAIT_BRANCH			\
	sub	pc, pc, #4

#define	CPWAIT(tmp)				\
	mrc	p15, 0, tmp, c2, c0, 0	/* arbitrary read of CP15 */;	\
	mov	tmp, tmp				/* wait for it to complete */;	\
	CPWAIT_BRANCH				/* branch to next insn */

#define MMU_ENABLE		0x01		/* MMU enable */

#define SDRAM_START		0xa0000000	/* SDRAM start address */
#define PAGETABLE		0xa0080000	/* L1 page table start address */

#define	L1_S_SIZE		0x00100000	/* 1M */
#define	L1_S_OFFSET		(L1_S_SIZE - 1)
#define	L1_S_FRAME		(~L1_S_OFFSET)
#define	L1_S_SHIFT		20

#define	L1_TYPE_S		0x02		/* Section */

/* L1 Section Descriptor */
#define	L1_S_B			0x00000004	/* bufferable Section */
#define	L1_S_C			0x00000008	/* cacheable Section */
#define	L1_S_IMP		0x00000010	/* implementation defined */
#define	L1_S_DOM(x)		((x) << 5)	/* domain */
#define	L1_S_DOM_MASK	L1_S_DOM(0xf)
#define	L1_S_AP(x)		((x) << 10)	/* access permissions */
#define	L1_S_ADDR_MASK	0xfff00000	/* phys address of section */

#define	L1_S_XSCALE_P	0x00000200	/* ECC enable for this section */
#define	L1_S_XSCALE_TEX(x) ((x) << 12)	/* Type Extension */

/*
 * Short-hand for common AP_* constants.
 *
 * Note: These values assume the S (System) bit is set and
 * the R (ROM) bit is clear in CP15 register 1.
 */
#define	AP_KR		0x00			/* kernel read */
#define	AP_KRW		0x01			/* kernel read/write */
#define	AP_KRWUR	0x02			/* kernel read/write usr read */
#define	AP_KRWURW	0x03			/* kernel read/write usr read/write */

/*
 * Domain Types for the Domain Access Control Register.
 */
#define	DOMAIN_FAULT	0x00		/* no access */
#define	DOMAIN_CLIENT	0x01		/* client */
#define	DOMAIN_RESERVED	0x02		/* reserved */
#define	DOMAIN_MANAGER	0x03		/* manager */

#define	PMAP_DOMAIN_KERNEL	15		/* The kernel uses domain #15 */

.globl lowlevel_init
lowlevel_init:
	/* init SCOOP GPCR */
	ldr r1, SCOOP_GPCR
	ldr r2, SCOOP_GPCR_VALUE
	str r2, [r1]
	
	/* init MMU */
	/* build page table */
	ldr	r0, startup_pagetable
	adr	r4, mmu_init_table
	b	3f

2:
	str	r3, [r0, r2]
	add	r2, r2, #4
	add	r3, r3, #(L1_S_SIZE)
	adds r1, r1, #-1
	bhi 2b
3:
	ldmia r4!, {r1,r2,r3}   /* # of sections, PA|attr, VA */
	cmp r1, #0
	bne 2b
	
	mcr	p15, 0, r0, c2, c0, 0	/* Set TTB */
	mcr	p15, 0, r0, c8, c7, 0	/* Flush TLB */
	
	/* Set the Domain Access register.  Very important! */
	mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
	mcr	p15, 0, r0, c3, c0, 0
	
	/* Enable MMU */
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #MMU_ENABLE
	mcr	p15, 0, r0, c1, c0, 0
	CPWAIT(r0)

	mov	pc, lr

SCOOP_GPCR		: .word 0x10800020
SCOOP_GPCR_VALUE: .word 0x3fe

#define MMU_INIT(va,pa,n_sec,attr) 			\
	.word	n_sec					    ; 	\
	.word	4*((va)>>L1_S_SHIFT)		; 	\
	.word	(pa)|(attr)				    ;

startup_pagetable:	.word	PAGETABLE
mmu_init_table:
	/* map VA 0x00000000..0x03ffffff to PA 0xa0000000..0xa3ffffff */
	MMU_INIT(0x00000000,  SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
	/* map SDRAM (0xa0000000) VA==PA, WT cacheable */
	MMU_INIT(SDRAM_START, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
	/* map 0x40000000 - 0x480fffff  N N N  Processor Registers */
	MMU_INIT(0x40000000, 0x40000000, 128, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
	/* map 0x10800000..0x10900000, 0x10800000..0x10900000*/
	MMU_INIT(0x10800000, 0x10800000, 1, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
	.word 0	/* end of table */

.globl set_turbo_mode
set_turbo_mode:
	/* turn on turbo mode */
	mrc	p14, 0, r2, c6, c0, 0
	orr	r2, r2, #0xB		/* Turbo, Fast-Bus, Freq change**/
	mcr	p14, 0, r2, c6, c0, 0

	mov	pc, lr