mcu_interface.v

FPGA与单片机接口

//----------------------???????-----------------------------
//wr-??????,rd-??????,ale-??????,rst-??,txen-,locxc-???
//addhigh-???8?,label-ID?,c8b-????
//run-???,watchdog-???,fckdata-????,fcktone-????,fckfe-?????,fckrser-???
module mcu_interface (wr,rd,ale,rst,txen,locxc,addhigh,label,c8b,run,fckdata,fcktone,fckfe,fckrser,emsloop,d);

input wr,rd,ale,rst,txen,locxc;
input [7:0]addhigh,label,c8b;
output run,fckdata,fcktone,fckfe,fckrser;
output emsloop;
inout [7:0]d;
reg emsloop,run;
reg [7:0]data_config,d_reg,labela;
reg [15:0]boardn_add_high[2:0],boardn_add_low[2:0],add;
reg [11:0]num_r;
reg [11:0]num_i;

wire fckdata,fcktone,fckfe;
wire [7:0]label;

always @(posedge locxc)
	begin
	labela=label;
	end
//-----------------------------------
always @(posedge locxc)
	begin
	if (txen==1)
		num_i=num_i+1;
	else
		num_i=0;
	   num_r=num_i-17;	
	end
//-------------------------------------------
assign d=(!rd)?d_reg:8'bz;
//-------------------------------------------
always@(negedge ale)//???
	add<={addhigh,d};
//-------------------------------------------
always @(rd)//????
	begin
	if(rd==0&&wr==1)
		begin
		case(add)
		    16'h0807 : d_reg<=labela;
			16'h0810 : d_reg<=boardn_add_high[0][7:0];
			16'h0811 : d_reg<=boardn_add_high[0][15:8];
			16'h0812 : d_reg<=boardn_add_low[0][7:0];
			16'h0813 : d_reg<=boardn_add_low[0][15:8];
			16'h0814 : d_reg<=boardn_add_high[1][7:0];
			16'h0815 : d_reg<=boardn_add_high[1][15:8];
			16'h0816 : d_reg<=boardn_add_low[1][7:0];
			16'h0817 : d_reg<=boardn_add_low[1][15:8];
			16'h0818 : d_reg<=boardn_add_high[2][7:0];
			16'h0819 : d_reg<=boardn_add_high[2][15:8];
			16'h081a : d_reg<=boardn_add_low[2][7:0];
			16'h081b : d_reg<=boardn_add_low[2][15:8];
			16'h0850 : d_reg<=data_config;
			16'h0880 : d_reg<=c8b;
            16'h0881 : d_reg<=!emsloop?c8b:8'b00000001;
			default	 : d_reg<=8'hff;
		endcase
		end
	end
//------------------------------------------------------
always @(wr)//????
	if (wr==0&&rd==1)
		case(add)
			16'h0800 : emsloop=d[0];
			16'h0808 : run=d[0];
			16'h0810 : boardn_add_high[0][7:0]=d;
			16'h0811 : boardn_add_high[0][15:8]=d;
			16'h0812 : boardn_add_low[0][7:0]=d;
			16'h0813 : boardn_add_low[0][15:8]=d;
			16'h0814 : boardn_add_high[1][7:0]=d;
			16'h0815 : boardn_add_high[1][15:8]=d;
			16'h0816 : boardn_add_low[1][7:0]=d;
			16'h0817 : boardn_add_low[1][15:8]=d;
			16'h0818 : boardn_add_high[2][7:0]=d;
			16'h0819 : boardn_add_high[2][15:8]=d;
			16'h081a : boardn_add_low[2][7:0]=d;
			16'h081b : boardn_add_low[2][15:8]=d;
			16'h0850 : data_config=d;
		endcase

assign fckdata=(num_r[11:1]>=boardn_add_high[0][10:0])&&(num_r[11:1]<=boardn_add_low[0][10:0]);
assign fcktone=(num_r[11:1]>=boardn_add_high[1][10:0])&&(num_r[11:1]<=boardn_add_low[1][10:0]);
assign fckfe=(num_r[11:1]>=boardn_add_high[2][10:0])&&(num_r[11:1]<=boardn_add_low[2][10:0]);
assign fckrser=!(fckdata && fcktone && fckfe);
endmodule