perf_cache.h

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/* <LIC_AMD_STD>
 * Copyright (c) 2005 Advanced Micro Devices, Inc.
 * 
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 * 
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 * 
 * The full GNU General Public License is included in this distribution in the
 * file called COPYING
 * </LIC_AMD_STD>  */
/* <CTL_AMD_STD>
 * </CTL_AMD_STD>  */
/* <DOC_AMD_STD>
 * </DOC_AMD_STD>  */
#ifndef __perf_cache_h__
#define __perf_cache_h__

#include <asm/cachectl.h>

#define AU_PERF_CNT_USER      0x4
#define AU_PERF_CNT_KERN      0x2
#define AU_PERF_CNT_INT       0x1
#define AU_PERF_CNT_ALL       0x7

// bus events
#define AU_PERF_LD_NC         0xd000
#define AU_PERF_LD_MISS       0xd010
#define AU_PERF_CASTOUT       0xd020
#define AU_PERF_IFETCH        0xd030
#define AU_PERF_IFETCH_NC     0xd040
#define AU_PERF_ST_MISS       0xd050
#define AU_PERF_REQ_NO_GNT    0xd060

// data cache events
#define AU_PERF_LD_HIT        0xa000
#define AU_PERF_ST_HIT        0xa010
#define AU_PERF_HIT_UNDER     0xa020
#define AU_PERF_REPLAY        0xa030
#define AU_PERF_SNP_HIT       0xa040
#define AU_PERF_SNP_GRAB      0xa050
#define AU_PERF_SNP_PUSH      0xa060
#define AU_PERF_AONLY         0xa070

#define MIPS_CACHE_AU_PERF    0x8000
#define AU_PERF_CLEAR         0xf000
#define AU_PERF_GET_VALUE     0xf010
//#define AU_PERF_SET_VALUE   0xf020
#define AU_PERF_GET_CONTROL   0xf030
//#define AU_PERF_SET_CONTROL 0xf040

#define AU_PERF_HI            0
#define AU_PERF_LO            1
#define AU_PERF_SET_HI(x)     ((x) << 16)
#define AU_PERF_SET_LO(x)     ((x) << 0)


#define MIPS_CACHE_IDX_INV_I             0x0 
#define MIPS_CACHE_IDX_WBI_D             0x1 
#define MIPS_CACHE_IDX_CASTOUT           0x1  // better name
//#define MIPS_CACHE_IDX_INV_SI          0x2
//#define MIPS_CACHE_IDX_WBI_SD          0x3
#define MIPS_CACHE_IDX_LOAD_TAG_I        0x4 
#define MIPS_CACHE_IDX_LOAD_TAG_D        0x5
//#define MIPS_CACHE_IDX_LOAD_TAG_SI     0x6
//#define MIPS_CACHE_IDX_LOAD_TAG_SD     0x7
#define MIPS_CACHE_IDX_STORE_TAG_I       0x8 
#define MIPS_CACHE_IDX_STORE_TAG_D       0x9
//#define MIPS_CACHE_IDX_STORE_TAG_SI    0xA
//#define MIPS_CACHE_IDX_STORE_TAG_SD    0xB
//#define MIPS_CACHE_CREATE_DIRTY_EXC_D  0xD
//#define MIPS_CACHE_CREATE_DIRTY_EXC_SD 0xF
#define MIPS_CACHE_HIT_INV_I             0x10
#define MIPS_CACHE_HIT_INV_D             0x11
//#define MIPS_CACHE_HIT_INV_SI          0x12
//#define MIPS_CACHE_HIT_INV_SD          0x13
#define MIPS_CACHE_FILL_I                0x14
#define MIPS_CACHE_HIT_WBI_D             0x15
#define MIPS_CACHE_CASTOUT               0x15 // better name
//#define MIPS_CACHE_HIT_WBI_SD          0x17
//#define MIPS_CACHE_HIT_WB_I            0x18 // what is this?
#define MIPS_CACHE_HIT_WB_D              0x19
//#define MIPS_CACHE_HIT_WB_SD           0x1B
//#define MIPS_CACHE_HIT_SET_VIRTUAL_SI  0x1E
//#define MIPS_CACHE_HIT_SET_VIRTUAL_SD  0x1F

#define PREF(x) asm volatile("pref 0, 0(%0)" :: "r"(x));
//#define PREF(x)

#endif