pciconstants.java

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	public static final int PCI_MEMORY_BASE = 0x20; /* Memory range behind */
	public static final int PCI_MEMORY_LIMIT = 0x22;
	public static final long PCI_MEMORY_RANGE_TYPE_MASK = 0x0fL;
	public static final long PCI_MEMORY_RANGE_MASK = (~0x0fL);
	public static final int PCI_PREF_MEMORY_BASE = 0x24; /* Prefetchable memory range behind */
	public static final int PCI_PREF_MEMORY_LIMIT = 0x26;
	public static final long PCI_PREF_RANGE_TYPE_MASK = 0x0fL;
	public static final int PCI_PREF_RANGE_TYPE_32 = 0x00;
	public static final int PCI_PREF_RANGE_TYPE_64 = 0x01;
	public static final long PCI_PREF_RANGE_MASK = (~0x0fL);
	public static final int PCI_PREF_BASE_UPPER32 = 0x28; /*
														   * Upper half of prefetchable memory
														   * range
														   */
	public static final int PCI_PREF_LIMIT_UPPER32 = 0x2c;
	public static final int PCI_IO_BASE_UPPER16 = 0x30; /* Upper half of I/O addresses */
	public static final int PCI_IO_LIMIT_UPPER16 = 0x32;
	/* = 0x34 same as for htype 0 */
	/* = 0x35-= 0x3b is reserved */
	public static final int PCI_ROM_ADDRESS1 = 0x38; /* Same as PCI_ROM_ADDRESS, but for htype 1 */
	/* = 0x3c-= 0x3d are same as for htype 0 */
	public static final int PCI_BRIDGE_CONTROL = 0x3e;
	public static final int PCI_BRIDGE_CTL_PARITY = 0x01; /*
														   * Enable parity detection on secondary
														   * interface
														   */
	public static final int PCI_BRIDGE_CTL_SERR = 0x02; /* The same for SERR forwarding */
	public static final int PCI_BRIDGE_CTL_NO_ISA = 0x04; /* Disable bridging of ISA ports */
	public static final int PCI_BRIDGE_CTL_VGA = 0x08; /* Forward VGA addresses */
	public static final int PCI_BRIDGE_CTL_MASTER_ABORT = 0x20; /* Report master aborts */
	public static final int PCI_BRIDGE_CTL_BUS_RESET = 0x40; /* Secondary bus reset */
	public static final int PCI_BRIDGE_CTL_FAST_BACK = 0x80; /*
															  * Fast Back2Back enabled on secondary
															  * interface
															  */

	/* Header type 2 (CardBus bridges) */
	public static final int PCI_CB_CAPABILITY_LIST = 0x14;
	/* = 0x15 reserved */
	public static final int PCI_CB_SEC_STATUS = 0x16; /* Secondary status */
	public static final int PCI_CB_PRIMARY_BUS = 0x18; /* PCI bus number */
	public static final int PCI_CB_CARD_BUS = 0x19; /* CardBus bus number */
	public static final int PCI_CB_SUBORDINATE_BUS = 0x1a; /* Subordinate bus number */
	public static final int PCI_CB_LATENCY_TIMER = 0x1b; /* CardBus latency timer */
	public static final int PCI_CB_MEMORY_BASE_0 = 0x1c;
	public static final int PCI_CB_MEMORY_LIMIT_0 = 0x20;
	public static final int PCI_CB_MEMORY_BASE_1 = 0x24;
	public static final int PCI_CB_MEMORY_LIMIT_1 = 0x28;
	public static final int PCI_CB_IO_BASE_0 = 0x2c;
	public static final int PCI_CB_IO_BASE_0_HI = 0x2e;
	public static final int PCI_CB_IO_LIMIT_0 = 0x30;
	public static final int PCI_CB_IO_LIMIT_0_HI = 0x32;
	public static final int PCI_CB_IO_BASE_1 = 0x34;
	public static final int PCI_CB_IO_BASE_1_HI = 0x36;
	public static final int PCI_CB_IO_LIMIT_1 = 0x38;
	public static final int PCI_CB_IO_LIMIT_1_HI = 0x3a;
	public static final long PCI_CB_IO_RANGE_MASK = (~0x03L);
	/* = 0x3c-= 0x3d are same as for htype 0 */
	public static final int PCI_CB_BRIDGE_CONTROL = 0x3e;
	public static final int PCI_CB_BRIDGE_CTL_PARITY = 0x01; /*
															  * Similar to standard bridge control
															  * register
															  */
	public static final int PCI_CB_BRIDGE_CTL_SERR = 0x02;
	public static final int PCI_CB_BRIDGE_CTL_ISA = 0x04;
	public static final int PCI_CB_BRIDGE_CTL_VGA = 0x08;
	public static final int PCI_CB_BRIDGE_CTL_MASTER_ABORT = 0x20;
	public static final int PCI_CB_BRIDGE_CTL_CB_RESET = 0x40; /* CardBus reset */
	public static final int PCI_CB_BRIDGE_CTL_16BIT_INT = 0x80; /*
																 * Enable interrupt for 16-bit
																 * cards
																 */
	public static final int PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 = 0x100; /*
																	  * Prefetch enable for both
																	  * memory regions
																	  */
	public static final int PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 = 0x200;
	public static final int PCI_CB_BRIDGE_CTL_POST_WRITES = 0x400;
	public static final int PCI_CB_SUBSYSTEM_VENDOR_ID = 0x40;
	public static final int PCI_CB_SUBSYSTEM_ID = 0x42;
	public static final int PCI_CB_LEGACY_MODE_BASE = 0x44; /*
															 * 16-bit PC Card legacy mode base
															 * address (ExCa)
															 */
	/* = 0x48-= 0x7f reserved */

	/* Capability lists */

	public static final int PCI_CAP_LIST_ID = 0; /* Capability ID */
	public static final int PCI_CAP_ID_PM = 0x01; /* Power Management */
	public static final int PCI_CAP_ID_AGP = 0x02; /* Accelerated Graphics Port */
	public static final int PCI_CAP_ID_VPD = 0x03; /* Vital Product Data */
	public static final int PCI_CAP_ID_SLOTID = 0x04; /* Slot Identification */
	public static final int PCI_CAP_ID_MSI = 0x05; /* Message Signalled Interrupts */
	public static final int PCI_CAP_ID_CHSWP = 0x06; /* CompactPCI HotSwap */
	public static final int PCI_CAP_LIST_NEXT = 1; /* Next capability in the list */
	public static final int PCI_CAP_FLAGS = 2; /* Capability defined flags (16 bits) */
	public static final int PCI_CAP_SIZEOF = 4;

	/* Power Management Registers */

	public static final int PCI_PM_PMC = 2; /* PM Capabilities Register */
	public static final int PCI_PM_CAP_VER_MASK = 0x0007; /* Version */
	public static final int PCI_PM_CAP_PME_CLOCK = 0x0008; /* PME clock required */
	public static final int PCI_PM_CAP_RESERVED = 0x0010; /* Reserved field */
	public static final int PCI_PM_CAP_DSI = 0x0020; /* Device specific initialization */
	public static final int PCI_PM_CAP_AUX_POWER = 0x01C0; /* Auxilliary power support mask */
	public static final int PCI_PM_CAP_D1 = 0x0200; /* D1 power state support */
	public static final int PCI_PM_CAP_D2 = 0x0400; /* D2 power state support */
	public static final int PCI_PM_CAP_PME = 0x0800; /* PME pin supported */
	public static final int PCI_PM_CAP_PME_MASK = 0xF800; /* PME Mask of all supported states */
	public static final int PCI_PM_CAP_PME_D0 = 0x0800; /* PME# from D0 */
	public static final int PCI_PM_CAP_PME_D1 = 0x1000; /* PME# from D1 */
	public static final int PCI_PM_CAP_PME_D2 = 0x2000; /* PME# from D2 */
	public static final int PCI_PM_CAP_PME_D3 = 0x4000; /* PME# from D3 (hot) */
	public static final int PCI_PM_CAP_PME_D3cold = 0x8000; /* PME# from D3 (cold) */
	public static final int PCI_PM_CTRL = 4; /* PM control and status register */
	public static final int PCI_PM_CTRL_STATE_MASK = 0x0003; /* Current power state (D0 to D3) */
	public static final int PCI_PM_CTRL_PME_ENABLE = 0x0100; /* PME pin enable */
	public static final int PCI_PM_CTRL_DATA_SEL_MASK = 0x1e00; /* Data select (??) */
	public static final int PCI_PM_CTRL_DATA_SCALE_MASK = 0x6000; /* Data scale (??) */
	public static final int PCI_PM_CTRL_PME_STATUS = 0x8000; /* PME pin status */
	public static final int PCI_PM_PPB_EXTENSIONS = 6; /* PPB support extensions (??) */
	public static final int PCI_PM_PPB_B2_B3 = 0x40; /* Stop clock when in D3hot (??) */
	public static final int PCI_PM_BPCC_ENABLE = 0x80; /* Bus power/clock control enable (??) */
	public static final int PCI_PM_DATA_REGISTER = 7; /* (??) */
	public static final int PCI_PM_SIZEOF = 8;

	/* AGP registers */

	public static final int PCI_AGP_VERSION = 2; /* BCD version number */
	public static final int PCI_AGP_RFU = 3; /* Rest of capability flags */
	public static final int PCI_AGP_STATUS = 4; /* Status register */
	public static final int PCI_AGP_STATUS_RQ_MASK = 0xff000000; /* Maximum number of requests - 1 */
	public static final int PCI_AGP_STATUS_SBA = 0x0200; /* Sideband addressing supported */
	public static final int PCI_AGP_STATUS_64BIT = 0x0020; /* 64-bit addressing supported */
	public static final int PCI_AGP_STATUS_FW = 0x0010; /* FW transfers supported */
	public static final int PCI_AGP_STATUS_RATE4 = 0x0004; /* 4x transfer rate supported */
	public static final int PCI_AGP_STATUS_RATE2 = 0x0002; /* 2x transfer rate supported */
	public static final int PCI_AGP_STATUS_RATE1 = 0x0001; /* 1x transfer rate supported */
	public static final int PCI_AGP_COMMAND = 8; /* Control register */
	public static final int PCI_AGP_COMMAND_RQ_MASK = 0xff000000; /*
																   * Master: Maximum number of
																   * requests
																   */
	public static final int PCI_AGP_COMMAND_SBA = 0x0200; /* Sideband addressing enabled */
	public static final int PCI_AGP_COMMAND_AGP = 0x0100; /* Allow processing of AGP transactions */
	public static final int PCI_AGP_COMMAND_64BIT = 0x0020; /* Allow processing of 64-bit addresses */
	public static final int PCI_AGP_COMMAND_FW = 0x0010; /* Force FW transfers */
	public static final int PCI_AGP_COMMAND_RATE4 = 0x0004; /* Use 4x rate */
	public static final int PCI_AGP_COMMAND_RATE2 = 0x0002; /* Use 2x rate */
	public static final int PCI_AGP_COMMAND_RATE1 = 0x0001; /* Use 1x rate */
	public static final int PCI_AGP_SIZEOF = 12;

	/* Slot Identification */

	public static final int PCI_SID_ESR = 2; /* Expansion Slot Register */
	public static final int PCI_SID_ESR_NSLOTS = 0x1f; /* Number of expansion slots available */
	public static final int PCI_SID_ESR_FIC = 0x20; /* First In Chassis Flag */
	public static final int PCI_SID_CHASSIS_NR = 3; /* Chassis Number */

	/* Message Signalled Interrupts registers */

	public static final int PCI_MSI_FLAGS = 2; /* Various flags */
	public static final int PCI_MSI_FLAGS_64BIT = 0x80; /* 64-bit addresses allowed */
	public static final int PCI_MSI_FLAGS_QSIZE = 0x70; /* Message queue size configured */
	public static final int PCI_MSI_FLAGS_QMASK = 0x0e; /* Maximum queue size available */
	public static final int PCI_MSI_FLAGS_ENABLE = 0x01; /* MSI feature enabled */
	public static final int PCI_MSI_RFU = 3; /* Rest of capability flags */
	public static final int PCI_MSI_ADDRESS_LO = 4; /* Lower 32 bits */
	public static final int PCI_MSI_ADDRESS_HI = 8; /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
	public static final int PCI_MSI_DATA_32 = 8; /* 16 bits of data for 32-bit devices */
	public static final int PCI_MSI_DATA_64 = 12; /* 16 bits of data for 64-bit devices */
}