pciconstants.java

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/*
 * $Id: PCIConstants.java,v 1.1 2003/11/25 11:41:21 epr Exp $
 */
package org.jnode.driver.pci;

/**
 * @author epr
 */
public interface PCIConstants {

	/** PCI Config address port */
	public static final int PW32_CONFIG_ADDRESS = 0xcf8;

	/** PCI Config data port */
	public static final int PRW32_CONFIG_DATA = 0xcfc;

	public static final int PCI_FIRST_PORT = PW32_CONFIG_ADDRESS;
	public static final int PCI_LAST_PORT = PRW32_CONFIG_DATA + 3;

	// --------------------------------
	// Header type constants

	/** Normal header type */
	public static final int HEADER_TYPE_NORMAL = 0;

	/** PCI-PCI bridge header type */
	public static final int HEADER_TYPE_BRIDGE = 1;

	/** Cardbus header type */
	public static final int HEADER_TYPE_CARDBUS = 2;

	// --------------------------------
	// Class constants

	public static final int CLASS_MASS_STORAGE_CONTROLLER = 0x01;
	public static final int SUBCLASS_MSC_SCSI = 0x00;
	public static final int SUBCLASS_MSC_IDE = 0x01;
	public static final int SUBCLASS_MSC_FLOPPY = 0x02;
	public static final int SUBCLASS_MSC_IPI = 0x03;
	public static final int SUBCLASS_MSC_OTHER = 0x80;

	public static final int CLASS_NETWORK_CONTROLLER = 0x02;
	public static final int SUBCLASS_NC_ETHERNET = 0x00;
	public static final int SUBCLASS_NC_TOKENRING = 0x01;
	public static final int SUBCLASS_NC_FDDI = 0x02;
	public static final int SUBCLASS_NC_OTHER = 0x80;

	public static final int CLASS_VIDEO_CONTROLLER = 0x03;
	public static final int SUBCLASS_VC_VGA = 0x00;
	public static final int SUBCLASS_VC_XGA = 0x01;
	public static final int SUBCLASS_VC_OTHER = 0x80;

	public static final int CLASS_MULTIMEDIA_CONTROLLER = 0x04;
	public static final int SUBCLASS_MMC_VIDEO = 0x00;
	public static final int SUBCLASS_MMC_AUDIO = 0x01;
	public static final int SUBCLASS_MMC_OTHER = 0x80;

	public static final int CLASS_MEMORY_CONTROLLER = 0x05;
	public static final int SUBCLASS_MEMC_RAM = 0x00;
	public static final int SUBCLASS_MEMC_FLASH = 0x01;
	public static final int SUBCLASS_MEMC_OTHER = 0x80;

	public static final int CLASS_BRIDGE = 0x06;
	public static final int SUBCLASS_BR_HOST = 0x00;
	public static final int SUBCLASS_BR_ISA = 0x01;
	public static final int SUBCLASS_BR_EISA = 0x02;
	public static final int SUBCLASS_BR_MCI = 0x03;
	public static final int SUBCLASS_BR_PCI = 0x04;
	public static final int SUBCLASS_BR_PCMCIA = 0x05;
	public static final int SUBCLASS_BR_OTHER = 0x80;

	/*
	 * Under PCI, each device has 256 bytes of configuration address space, of which the first 64
	 * bytes are standardized as follows:
	 */
	public static final int PCI_VENDOR_ID = 0x00; /* 16 bits */
	public static final int PCI_DEVICE_ID = 0x02; /* 16 bits */
	public static final int PCI_COMMAND = 0x04; /* 16 bits */
	public static final int PCI_COMMAND_IO = 0x1; /* Enable response in I/O space */
	public static final int PCI_COMMAND_MEMORY = 0x2; /* Enable response in Memory space */
	public static final int PCI_COMMAND_MASTER = 0x4; /* Enable bus mastering */
	public static final int PCI_COMMAND_SPECIAL = 0x8; /* Enable response to special cycles */
	public static final int PCI_COMMAND_INVALIDATE = 0x10; /* Use memory write and invalidate */
	public static final int PCI_COMMAND_VGA_PALETTE = 0x20; /* Enable palette snooping */
	public static final int PCI_COMMAND_PARITY = 0x40; /* Enable parity checking */
	public static final int PCI_COMMAND_WAIT = 0x80; /* Enable address/data stepping */
	public static final int PCI_COMMAND_SERR = 0x100; /* Enable SERR */
	public static final int PCI_COMMAND_FAST_BACK = 0x200; /* Enable back-to-back writes */

	public static final int PCI_STATUS = 0x06; /* 16 bits */
	public static final int PCI_STATUS_CAP_LIST = 0x10; /* Support Capability List */
	public static final int PCI_STATUS_66MHZ = 0x20; /* Support 66 Mhz PCI 2.1 bus */
	public static final int PCI_STATUS_UDF = 0x40; /* Support User Definable Features [obsolete] */
	public static final int PCI_STATUS_FAST_BACK = 0x80; /* Accept fast-back to back */
	public static final int PCI_STATUS_PARITY = 0x100; /* Detected parity error */
	public static final int PCI_STATUS_DEVSEL_MASK = 0x600; /* DEVSEL timing */
	public static final int PCI_STATUS_DEVSEL_FAST = 0x000;
	public static final int PCI_STATUS_DEVSEL_MEDIUM = 0x200;
	public static final int PCI_STATUS_DEVSEL_SLOW = 0x400;
	public static final int PCI_STATUS_SIG_TARGET_ABORT = 0x800; /* Set on target abort */
	public static final int PCI_STATUS_REC_TARGET_ABORT = 0x1000; /* Master ack of " */
	public static final int PCI_STATUS_REC_MASTER_ABORT = 0x2000; /* Set on master abort */
	public static final int PCI_STATUS_SIG_SYSTEM_ERROR = 0x4000; /* Set when we drive SERR */
	public static final int PCI_STATUS_DETECTED_PARITY = 0x8000; /* Set on parity error */

	public static final int PCI_CLASS_REVISION = 0x08; /*
													    * High 24 bits are class, low 8
													    */
	public static final int PCI_REVISION_ID = 0x08; /* Revision ID */
	public static final int PCI_CLASS_PROG = 0x09; /* Reg. Level Programming Interface */
	public static final int PCI_CLASS_DEVICE = 0x0a; /* Device class */

	public static final int PCI_CACHE_LINE_SIZE = 0x0c; /* 8 bits */
	public static final int PCI_LATENCY_TIMER = 0x0d; /* 8 bits */
	public static final int PCI_HEADER_TYPE = 0x0e; /* 8 bits */
	public static final int PCI_HEADER_TYPE_NORMAL = 0;
	public static final int PCI_HEADER_TYPE_BRIDGE = 1;
	public static final int PCI_HEADER_TYPE_CARDBUS = 2;

	public static final int PCI_BIST = 0x0f; /* 8 bits */
	public static final int PCI_BIST_CODE_MASK = 0x0f; /* Return result */
	public static final int PCI_BIST_START = 0x40; /* 1 to start BIST, 2 secs or less */
	public static final int PCI_BIST_CAPABLE = 0x80; /* 1 if BIST capable */

	/*
	 * Base addresses specify locations in memory or I/O space. Decoded size can be determined by
	 * writing a value of = 0xffffffff to the register, and reading it back. Only 1 bits are
	 * decoded.
	 */
	public static final int PCI_BASE_ADDRESS_0 = 0x10; /* 32 bits */
	public static final int PCI_BASE_ADDRESS_1 = 0x14; /* 32 bits [htype 0,1 only] */
	public static final int PCI_BASE_ADDRESS_2 = 0x18; /* 32 bits [htype 0 only] */
	public static final int PCI_BASE_ADDRESS_3 = 0x1c; /* 32 bits */
	public static final int PCI_BASE_ADDRESS_4 = 0x20; /* 32 bits */
	public static final int PCI_BASE_ADDRESS_5 = 0x24; /* 32 bits */
	public static final int PCI_BASE_ADDRESS_SPACE = 0x01; /* 0 = memory, 1 = I/O */
	public static final int PCI_BASE_ADDRESS_SPACE_IO = 0x01;
	public static final int PCI_BASE_ADDRESS_SPACE_MEMORY = 0x00;
	public static final int PCI_BASE_ADDRESS_MEM_TYPE_MASK = 0x06;
	public static final int PCI_BASE_ADDRESS_MEM_TYPE_32 = 0x00; /* 32 bit address */
	public static final int PCI_BASE_ADDRESS_MEM_TYPE_1M = 0x02; /* Below 1M [obsolete] */
	public static final int PCI_BASE_ADDRESS_MEM_TYPE_64 = 0x04; /* 64 bit address */
	public static final int PCI_BASE_ADDRESS_MEM_PREFETCH = 0x08; /* prefetchable? */
	public static final long PCI_BASE_ADDRESS_MEM_MASK = (~0x0fL);
	public static final long PCI_BASE_ADDRESS_IO_MASK = (~0x03L);
	/* bit 1 is reserved if address_space = 1 */

	/* Header type 0 (normal devices) */
	public static final int PCI_CARDBUS_CIS = 0x28;
	public static final int PCI_SUBSYSTEM_VENDOR_ID = 0x2c;
	public static final int PCI_SUBSYSTEM_ID = 0x2e;
	public static final int PCI_ROM_ADDRESS = 0x30; /* Bits 31..11 are address, 10..1 reserved */
	public static final int PCI_ROM_ADDRESS_ENABLE = 0x01;
	public static final long PCI_ROM_ADDRESS_MASK = (~0x7ffL);

	public static final int PCI_CAPABILITY_LIST = 0x34; /* Offset of first capability list entry */

	/* = 0x35-= 0x3b are reserved */
	public static final int PCI_INTERRUPT_LINE = 0x3c; /* 8 bits */
	public static final int PCI_INTERRUPT_PIN = 0x3d; /* 8 bits */
	public static final int PCI_MIN_GNT = 0x3e; /* 8 bits */
	public static final int PCI_MAX_LAT = 0x3f; /* 8 bits */

	/* Header type 1 (PCI-to-PCI bridges) */
	public static final int PCI_PRIMARY_BUS = 0x18; /* Primary bus number */
	public static final int PCI_SECONDARY_BUS = 0x19; /* Secondary bus number */
	public static final int PCI_SUBORDINATE_BUS = 0x1a; /* Highest bus number behind the bridge */
	public static final int PCI_SEC_LATENCY_TIMER = 0x1b; /* Latency timer for secondary interface */
	public static final int PCI_IO_BASE = 0x1c; /* I/O range behind the bridge */
	public static final int PCI_IO_LIMIT = 0x1d;
	public static final long PCI_IO_RANGE_TYPE_MASK = 0x0fL; /* I/O bridging type */
	public static final int PCI_IO_RANGE_TYPE_16 = 0x00;
	public static final int PCI_IO_RANGE_TYPE_32 = 0x01;
	public static final long PCI_IO_RANGE_MASK = (~0x0fl);
	public static final int PCI_SEC_STATUS = 0x1e; /* Secondary status register, only bit 14 used */