nvidiaacceleration.java
来自「纯java操作系统jnode,安装简单和操作简单的个人使用的Java操作系统」· Java 代码 · 共 856 行 · 第 1/3 页
JAVA
856 行
setACC(NVACC_PR_CTX0_2, 0x01008018); /* NVclass $018, patchcfg ROP_AND, nv10+: little endian */
setACC(NVACC_PR_CTX2_2, 0x00000000); /* DMA0 and DMA1 instance invalid */
setACC(NVACC_PR_CTX3_2, 0x00000000); /* method traps disabled */
/* (setup set '3') */
setACC(NVACC_PR_CTX0_3, 0x01008021); /* NVclass $021, patchcfg ROP_AND, nv10+: little endian */
setACC(NVACC_PR_CTX2_3, 0x00000000); /* DMA0 and DMA1 instance invalid */
setACC(NVACC_PR_CTX3_3, 0x00000000); /* method traps disabled */
/* (setup set '4') */
setACC(NVACC_PR_CTX0_4, 0x0100805f); /* NVclass $05f, patchcfg ROP_AND, nv10+: little endian */
setACC(NVACC_PR_CTX2_4, 0x00000000); /* DMA0 and DMA1 instance invalid */
setACC(NVACC_PR_CTX3_4, 0x00000000); /* method traps disabled */
/* (setup set '5') */
setACC(NVACC_PR_CTX0_5, 0x0100804b); /* NVclass $04b, patchcfg ROP_AND, nv10+: little endian */
setACC(NVACC_PR_CTX2_5, 0x00000000); /* DMA0 and DMA1 instance invalid */
setACC(NVACC_PR_CTX3_5, 0x00000000); /* method traps disabled */
/* (setup set '6') */
setACC(NVACC_PR_CTX0_6, 0x0100a048);
/*
* NVclass $048, patchcfg ROP_AND, userclip enable, nv10+: little endian
*/
setACC(NVACC_PR_CTX1_6, 0x00000d01); /* format is A8RGB24, MSB mono */
setACC(NVACC_PR_CTX2_6, 0x11401140); /* DMA0, DMA1 instance = $1140 */
setACC(NVACC_PR_CTX3_6, 0x00000000); /* method traps disabled */
/* (setup set '7') */
if (architecture != NV04A) {
setACC(NVACC_PR_CTX0_7, 0x0300a094);
/*
* NVclass $094, patchcfg ROP_AND, userclip enable, context surface0 valid, nv10+: little endian
*/
} else {
setACC(NVACC_PR_CTX0_7, 0x0300a054);
/*
* NVclass $054, patchcfg ROP_AND, userclip enable, context surface0 valid
*/
}
setACC(NVACC_PR_CTX1_7, 0x00000d01); /* format is A8RGB24, MSB mono */
setACC(NVACC_PR_CTX2_7, 0x11401140); /* DMA0, DMA1 instance = $1140 */
setACC(NVACC_PR_CTX3_7, 0x00000000); /* method traps disabled */
/* (setup set '8') */
if (architecture != NV04A) {
setACC(NVACC_PR_CTX0_8, 0x0300a095);
/*
* NVclass $095, patchcfg ROP_AND, userclip enable, context surface0 valid, nv10+: little endian
*/
} else {
setACC(NVACC_PR_CTX0_8, 0x0300a055);
/*
* NVclass $055, patchcfg ROP_AND, userclip enable, context surface0 valid
*/
}
setACC(NVACC_PR_CTX1_8, 0x00000d01); /* format is A8RGB24, MSB mono */
setACC(NVACC_PR_CTX2_8, 0x11401140); /* DMA0, DMA1 instance = $1140 */
setACC(NVACC_PR_CTX3_8, 0x00000000); /* method traps disabled */
/* (setup set '9') */
setACC(NVACC_PR_CTX0_9, 0x00000058); /* NVclass $058, nv10+: little endian */
setACC(NVACC_PR_CTX2_9, 0x11401140); /* DMA0, DMA1 instance = $1140 */
setACC(NVACC_PR_CTX3_9, 0x00000000); /* method traps disabled */
/* (setup set 'A') */
setACC(NVACC_PR_CTX0_A, 0x00000059); /* NVclass $059, nv10+: little endian */
setACC(NVACC_PR_CTX2_A, 0x11401140); /* DMA0, DMA1 instance = $1140 */
setACC(NVACC_PR_CTX3_A, 0x00000000); /* method traps disabled */
/* (setup set 'B') */
setACC(NVACC_PR_CTX0_B, 0x0000005a); /* NVclass $05a, nv10+: little endian */
setACC(NVACC_PR_CTX2_B, 0x11401140); /* DMA0, DMA1 instance = $1140 */
setACC(NVACC_PR_CTX3_B, 0x00000000); /* method traps disabled */
/* (setup set 'C') */
setACC(NVACC_PR_CTX0_C, 0x0000005b); /* NVclass $05b, nv10+: little endian */
setACC(NVACC_PR_CTX2_C, 0x11401140); /* DMA0, DMA1 instance = $1140 */
setACC(NVACC_PR_CTX3_C, 0x00000000); /* method traps disabled */
/* (setup set 'D') */
if (architecture != NV04A) {
setACC(NVACC_PR_CTX0_D, 0x00000093); /* NVclass $093, nv10+: little endian */
} else {
setACC(NVACC_PR_CTX0_D, 0x0300a01c);
/*
* NVclass $01c, patchcfg ROP_AND, userclip enable, context surface0 valid
*/
}
setACC(NVACC_PR_CTX2_D, 0x11401140); /* DMA0, DMA1 instance = $1140 */
setACC(NVACC_PR_CTX3_D, 0x00000000); /* method traps disabled */
/* (setup set 'E' if needed) */
if (architecture != NV04A) {
setACC(NVACC_PR_CTX0_E, 0x0300a01c);
/*
* NVclass $01c, patchcfg ROP_AND, userclip enable, context surface0 valid, nv10+: little endian
*/
setACC(NVACC_PR_CTX2_E, 0x11401140); /* DMA0, DMA1 instance = $1140 */
setACC(NVACC_PR_CTX3_E, 0x00000000); /* method traps disabled */
}
/** * PGRAPH ** */
if (architecture != NV04A) {
/* set resetstate for most function blocks */
setACC(NVACC_DEBUG0, 0x0003ffff);
/* init some function blocks */
setACC(NVACC_DEBUG1, 0x00118701);
setACC(NVACC_DEBUG2, 0x24f82ad9);
setACC(NVACC_DEBUG3, 0x55de0030);
/* end resetstate for the function blocks */
setACC(NVACC_DEBUG0, 0x00000000);
/* disable specific functions */
setACC(NVACC_NV10_DEBUG4, 0);
} else {
/* init some function blocks */
setACC(NVACC_DEBUG0, 0x1231c001);
setACC(NVACC_DEBUG1, 0x72111101);
setACC(NVACC_DEBUG2, 0x11d5f071);
setACC(NVACC_DEBUG3, 0x10d4ff31);
}
/* reset all cache sets */
setACC(NVACC_CACHE1_1, 0);
setACC(NVACC_CACHE1_2, 0);
setACC(NVACC_CACHE1_3, 0);
setACC(NVACC_CACHE1_4, 0);
setACC(NVACC_CACHE1_5, 0);
setACC(NVACC_CACHE2_1, 0);
setACC(NVACC_CACHE2_2, 0);
setACC(NVACC_CACHE2_3, 0);
setACC(NVACC_CACHE2_4, 0);
setACC(NVACC_CACHE2_5, 0);
setACC(NVACC_CACHE3_1, 0);
setACC(NVACC_CACHE3_2, 0);
setACC(NVACC_CACHE3_3, 0);
setACC(NVACC_CACHE3_4, 0);
setACC(NVACC_CACHE3_5, 0);
setACC(NVACC_CACHE4_1, 0);
setACC(NVACC_CACHE4_2, 0);
setACC(NVACC_CACHE4_3, 0);
setACC(NVACC_CACHE4_4, 0);
setACC(NVACC_CACHE4_5, 0);
if (architecture != NV04A)
setACC(NVACC_NV10_CACHE5_1, 0);
setACC(NVACC_CACHE5_2, 0);
setACC(NVACC_CACHE5_3, 0);
setACC(NVACC_CACHE5_4, 0);
setACC(NVACC_CACHE5_5, 0);
if (architecture != NV04A)
setACC(NVACC_NV10_CACHE6_1, 0);
setACC(NVACC_CACHE6_2, 0);
setACC(NVACC_CACHE6_3, 0);
setACC(NVACC_CACHE6_4, 0);
setACC(NVACC_CACHE6_5, 0);
if (architecture != NV04A)
setACC(NVACC_NV10_CACHE7_1, 0);
setACC(NVACC_CACHE7_2, 0);
setACC(NVACC_CACHE7_3, 0);
setACC(NVACC_CACHE7_4, 0);
setACC(NVACC_CACHE7_5, 0);
if (architecture != NV04A)
setACC(NVACC_NV10_CACHE8_1, 0);
setACC(NVACC_CACHE8_2, 0);
setACC(NVACC_CACHE8_3, 0);
setACC(NVACC_CACHE8_4, 0);
setACC(NVACC_CACHE8_5, 0);
if (architecture != NV04A) {
/* reset (disable) context switch stuff */
setACC(NVACC_NV10_CTX_SW1, 0);
setACC(NVACC_NV10_CTX_SW2, 0);
setACC(NVACC_NV10_CTX_SW3, 0);
setACC(NVACC_NV10_CTX_SW4, 0);
setACC(NVACC_NV10_CTX_SW5, 0);
}
/* setup accesible card memory range for acc engine */
setACC(NVACC_BBASE0, 0x00000000);
setACC(NVACC_BBASE1, 0x00000000);
setACC(NVACC_BBASE2, 0x00000000);
setACC(NVACC_BBASE3, 0x00000000);
setACC(NVACC_BLIMIT0, ((memorySize << 20) - 1));
setACC(NVACC_BLIMIT1, ((memorySize << 20) - 1));
setACC(NVACC_BLIMIT2, ((memorySize << 20) - 1));
setACC(NVACC_BLIMIT3, ((memorySize << 20) - 1));
if (architecture >= NV10A) {
setACC(NVACC_NV10_BBASE4, 0x00000000);
setACC(NVACC_NV10_BBASE5, 0x00000000);
setACC(NVACC_NV10_BLIMIT4, ((memorySize << 20) - 1));
setACC(NVACC_NV10_BLIMIT5, ((memorySize << 20) - 1));
}
if (architecture >= NV20A) {
/*
* fixme(?): assuming more BLIMIT registers here: Then how about BBASE6-9? (linux fixed value 'BLIMIT6-9' 0x01ffffff)
*/
setACC(NVACC_NV20_BLIMIT6, ((memorySize << 20) - 1));
setACC(NVACC_NV20_BLIMIT7, ((memorySize << 20) - 1));
setACC(NVACC_NV20_BLIMIT8, ((memorySize << 20) - 1));
setACC(NVACC_NV20_BLIMIT9, ((memorySize << 20) - 1));
}
/* disable all acceleration engine INT reguests */
setACC(NVACC_ACC_INTE, 0x00000000);
/* reset all acceration engine INT status bits */
setACC(NVACC_ACC_INTS, 0xffffffff);
if (architecture != NV04A) {
/* context control enabled */
setACC(NVACC_NV10_CTX_CTRL, 0x10010100);
/* all acceleration buffers, pitches and colors are valid */
setACC(NVACC_NV10_ACC_STAT, 0xffffffff);
} else {
/* context control enabled */
setACC(NVACC_NV04_CTX_CTRL, 0x10010100);
/* all acceleration buffers, pitches and colors are valid */
setACC(NVACC_NV04_ACC_STAT, 0xffffffff);
}
/* enable acceleration engine command FIFO */
setACC(NVACC_FIFO_EN, 0x00000001);
/* pattern shape value = 8x8, 2 color */
setACC(NVACC_PAT_SHP, 0x00000000);
if (architecture != NV04A) {
/* surface type is non-swizzle */
setACC(NVACC_NV10_SURF_TYP, 0x00000001);
} else {
/* surface type is non-swizzle */
setACC(NVACC_NV04_SURF_TYP, 0x00000001);
}
/* Set pixel width and format */
switch (bitsPerPixel) {
case 8 :
/* acc engine */
setACC(NVACC_FORMATS, 0x00001010);
if (architecture < NV30A)
setACC(NVACC_BPIXEL, 0x00111111); /* set depth 0-5: 4 bits per color */
else
setACC(NVACC_BPIXEL, 0x00000021); /* set depth 0-1: 5 bits per color */
setACC(NVACC_STRD_FMT, 0x03020202);
/* PRAMIN */
setACC(NVACC_PR_CTX1_0, 0x00000302); /* format is X24Y8, LSB mono */
setACC(NVACC_PR_CTX1_1, 0x00000302); /* format is X24Y8, LSB mono */
setACC(NVACC_PR_CTX1_2, 0x00000202); /* format is X16A8Y8, LSB mono */
setACC(NVACC_PR_CTX1_3, 0x00000302); /* format is X24Y8, LSB mono */
setACC(NVACC_PR_CTX1_4, 0x00000302); /* format is X24Y8, LSB mono */
setACC(NVACC_PR_CTX1_5, 0x00000302); /* format is X24Y8, LSB mono */
setACC(NVACC_PR_CTX1_9, 0x00000302); /* format is X24Y8, LSB mono */
setACC(NVACC_PR_CTX2_9, 0x00000302); /* dma_instance 0 valid, instance 1 invalid */
setACC(NVACC_PR_CTX1_B, 0x00000000); /* format is invalid */
setACC(NVACC_PR_CTX1_C, 0x00000000); /* format is invalid */
if (architecture == NV04A) {
setACC(NVACC_PR_CTX1_D, 0x00000302); /* format is X24Y8, LSB mono */
} else {
setACC(NVACC_PR_CTX1_D, 0x00000000); /* format is invalid */
setACC(NVACC_PR_CTX1_E, 0x00000302); /* format is X24Y8, LSB mono */
}
break;
case 15 :
/* acc engine */
setACC(NVACC_FORMATS, 0x00002071);
if (architecture < NV30A)
setACC(NVACC_BPIXEL, 0x00226222); /* set depth 0-5: 4 bits per color */
else
setACC(NVACC_BPIXEL, 0x00000042); /* set depth 0-1: 5 bits per color */
setACC(NVACC_STRD_FMT, 0x09080808);
/* PRAMIN */
setACC(NVACC_PR_CTX1_0, 0x00000902); /* format is X17RGB15, LSB mono */
setACC(NVACC_PR_CTX1_1, 0x00000902); /* format is X17RGB15, LSB mono */
setACC(NVACC_PR_CTX1_2, 0x00000802); /* format is X16A1RGB15, LSB mono */
setACC(NVACC_PR_CTX1_3, 0x00000902); /* format is X17RGB15, LSB mono */
setACC(NVACC_PR_CTX1_4, 0x00000902); /* format is X17RGB15, LSB mono */
setACC(NVACC_PR_CTX1_5, 0x00000902); /* format is X17RGB15, LSB mono */
setACC(NVACC_PR_CTX1_9, 0x00000902); /* format is X17RGB15, LSB mono */
setACC(NVACC_PR_CTX2_9, 0x00000902); /* dma_instance 0 valid, instance 1 invalid */
if (architecture == NV04A) {
setACC(NVACC_PR_CTX1_B, 0x00000702); /* format is X1RGB15, LSB mono */
setACC(NVACC_PR_CTX1_C, 0x00000702); /* format is X1RGB15, LSB mono */
} else {
setACC(NVACC_PR_CTX1_B, 0x00000902); /* format is X17RGB15, LSB mono */
setACC(NVACC_PR_CTX1_C, 0x00000902); /* format is X17RGB15, LSB mono */
setACC(NVACC_PR_CTX1_E, 0x00000902); /* format is X17RGB15, LSB mono */
}
setACC(NVACC_PR_CTX1_D, 0x00000902); /* format is X17RGB15, LSB mono */
break;
case 16 :
/* acc engine */
setACC(NVACC_FORMATS, 0x000050C2);
if (architecture < NV30A)
setACC(NVACC_BPIXEL, 0x00556555); /* set depth 0-5: 4 bits per color */
else
setACC(NVACC_BPIXEL, 0x000000a5); /* set depth 0-1: 5 bits per color */
if (architecture == NV04A)
setACC(NVACC_STRD_FMT, 0x0c0b0b0b);
else
setACC(NVACC_STRD_FMT, 0x000b0b0c);
/* PRAMIN */
setACC(NVACC_PR_CTX1_0, 0x00000c02); /* format is X16RGB16, LSB mono */
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