nvidiaacceleration.java
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JAVA
856 行
/*
* $Id: NVidiaAcceleration.java,v 1.1 2004/01/04 11:01:58 epr Exp $
*/
package org.jnode.driver.video.nvidia;
/**
* Hardware acceleration driver for NVidia video cards.
*
* This class has been made possible with big help from
* <a href="http://web.inter.nl.net/users/be-hold/BeOS/NVdriver/">Rudolf Cornelissen</a>.
*
* @author Ewout Prangsma (epr@users.sourceforge.net)
*/
public class NVidiaAcceleration implements NVidiaConstants {
/** NVidia card io */
private final NVidiaVgaIO io;
/** Card architecture */
private final int architecture;
/**
* Initialize this instance.
*
* @param io
*/
public NVidiaAcceleration(NVidiaVgaIO io, int architecture) {
this.io = io;
this.architecture = architecture;
}
/**
* rectangle fill - i.e. workspace and window background color span fill.
* i.e. (selected) menuitem background color (Dano)
*/
public void setupRectangle(int color) {
/*
* setup solid pattern: wait for room in fifo for pattern cmd if needed. (fifo holds 256 32bit words: count those, not bytes)
*/
while (((io.getReg16(NV16_PAT_FIFOFREE)) >> 2) < 5) {
/* snooze a bit so I do not hammer the bus */
snooze(10);
}
/* now setup pattern (writing 5 32bit words) */
setACC(NVACC_PAT_SHAPE, 0); /* 0 = 8x8, 1 = 64x1, 2 = 1x64 */
setACC(NVACC_PAT_COLOR0, 0xffffffff);
setACC(NVACC_PAT_COLOR1, 0xffffffff);
setACC(NVACC_PAT_MONO1, 0xffffffff);
setACC(NVACC_PAT_MONO2, 0xffffffff);
/*
* ROP3 registers (Raster OPeration): wait for room in fifo for ROP cmd if needed. (fifo holds 256 32bit words: count those, not bytes)
*/
while (((io.getReg16(NV16_ROP_FIFOFREE)) >> 2) < 1) {
/* snooze a bit so I do not hammer the bus */
snooze(10);
}
/* now setup ROP (writing 1 32bit word) for GXcopy */
setACC(NVACC_ROP_ROP3, 0xcc);
/*
* setup fill color: wait for room in fifo for bitmap cmd if needed. (fifo holds 256 32bit words: count those, not bytes)
*/
while (((io.getReg16(NV16_BMP_FIFOFREE)) >> 2) < 1) {
/* snooze a bit so I do not hammer the bus */
snooze(10);
}
/* now setup color (writing 1 32bit word) */
setACC(NVACC_BMP_COLOR1A, color);
}
/**
* Fill a rectangle with the color setup by {@link #setupRectangle(int)}.
*
* @param x
* @param y
* @param w
* @param h
*/
public void fillRectangle(int x, int y, int w, int h) {
/*
* instruct engine what to fill: wait for room in fifo for bitmap cmd if needed. (fifo holds 256 32bit words: count those, not bytes)
*/
while (((io.getReg16(NV16_BMP_FIFOFREE)) >> 2) < 2) {
/* snooze a bit so I do not hammer the bus */
snooze(10);
}
/* now setup fill (writing 2 32bit words) */
setACC(NVACC_BMP_UCRECTL_0, ((x << 16) | (y & 0x0000ffff)));
setACC(NVACC_BMP_UCRECSZ_0, (((w) << 16) | (h & 0x0000ffff)));
}
/**
* Setup for rectangle invert - i.e. text cursor and text selection.
*/
public void setupInvertRectangle() {
/*
* setup solid pattern: wait for room in fifo for pattern cmd if needed. (fifo holds 256 32bit words: count those, not bytes)
*/
while (((io.getReg16(NV16_PAT_FIFOFREE)) >> 2) < 5) {
/* snooze a bit so I do not hammer the bus */
snooze(10);
}
/* now setup pattern (writing 5 32bit words) */
setACC(NVACC_PAT_SHAPE, 0); /* 0 = 8x8, 1 = 64x1, 2 = 1x64 */
setACC(NVACC_PAT_COLOR0, 0xffffffff);
setACC(NVACC_PAT_COLOR1, 0xffffffff);
setACC(NVACC_PAT_MONO1, 0xffffffff);
setACC(NVACC_PAT_MONO2, 0xffffffff);
/*
* ROP3 registers (Raster OPeration): wait for room in fifo for ROP cmd if needed. (fifo holds 256 32bit words: count those, not bytes)
*/
while (((io.getReg16(NV16_ROP_FIFOFREE)) >> 2) < 1) {
/* snooze a bit so I do not hammer the bus */
snooze(10);
}
/* now setup ROP (writing 1 32bit word) for GXinvert */
setACC(NVACC_ROP_ROP3, 0x55);
/*
* reset fill color: wait for room in fifo for bitmap cmd if needed. (fifo holds 256 32bit words: count those, not bytes)
*/
while (((io.getReg16(NV16_BMP_FIFOFREE)) >> 2) < 1) {
/* snooze a bit so I do not hammer the bus */
snooze(10);
}
/* now reset color (writing 1 32bit word) */
setACC(NVACC_BMP_COLOR1A, 0);
}
/**
* Invert a given rectangle.
* Call {@link #setupInvertRectangle()} first.
*
* @param x
* @param y
* @param w
* @param h
*/
public void invertRectangle(int x, int y, int w, int h) {
/*
* instruct engine what to invert: wait for room in fifo for bitmap cmd if needed. (fifo holds 256 32bit words: count those, not bytes)
*/
while (((io.getReg16(NV16_BMP_FIFOFREE)) >> 2) < 2) {
/* snooze a bit so I do not hammer the bus */
snooze(10);
}
/* now setup invert (writing 2 32bit words) */
setACC(NVACC_BMP_UCRECTL_0, ((x << 16) | (y & 0x0000ffff)));
setACC(NVACC_BMP_UCRECSZ_0, (((w) << 16) | (h & 0x0000ffff)));
}
/**
* Engine required init. AFAIK this must be done for every new screenmode.
*
* @param frameBufferOffset
* Offset of active screen in framebuffer
* @param bytesPerRow
* The number of bytes per row
* @param memorySize
* The size of the cards memory in MB
* @param bitsPerPixel
* The number of bits per pixel (8, 15, 16, 32)
*/
public void accInit(int frameBufferOffset, int bytesPerRow, int memorySize, int bitsPerPixel) {
/* setup PTIMER: */
/* set timer numerator to 8 (in b0-15) */
setACC(NVACC_PT_NUMERATOR, 0x00000008);
/* set timer denominator to 3 (in b0-15) */
setACC(NVACC_PT_DENOMINATR, 0x00000003);
/* disable timer-alarm INT requests (b0) */
setACC(NVACC_PT_INTEN, 0x00000000);
/* reset timer-alarm INT status bit (b0) */
setACC(NVACC_PT_INTSTAT, 0xffffffff);
/* enable PRAMIN write access on pre NV10 before programming it! */
if (architecture == NV04A) {
/* set framebuffer config: type = notiling, PRAMIN write access enabled */
io.setReg32(NV32_PFB_CONFIG_0, 0x00001114);
}
/** * PFIFO ** */
/* (setup caches) */
/* disable caches reassign */
setACC(NVACC_PF_CACHES, 0x00000000);
/* cache1 push0 access disabled */
setACC(NVACC_PF_CACH1_PSH0, 0x00000000);
/* cache1 pull0 access disabled */
setACC(NVACC_PF_CACH1_PUL0, 0x00000000);
/* cache1 push1 mode = pio */
setACC(NVACC_PF_CACH1_PSH1, 0x00000000);
/* cache1 DMA instance adress = 0 (b0-15) */
setACC(NVACC_PF_CACH1_DMAI, 0x00000000);
/* cache0 push0 access disabled */
setACC(NVACC_PF_CACH0_PSH0, 0x00000000);
/* cache0 pull0 access disabled */
setACC(NVACC_PF_CACH0_PUL0, 0x00000000);
/*
* RAM HT (hash table(?)) baseadress = $10000 (b4-8), size = 4k, search = 128 (byte offset between hash 'sets'(?))
*/
/* (note: so(?) HT base is $00710000, last is $00710fff) */
setACC(NVACC_PF_RAMHT, 0x03000100);
/* RAM FC baseadress = $11000 (b3-8) (size is fixed to 0.5k(?)) */
/* (note: so(?) FC base is $00711000, last is $007111ff) */
setACC(NVACC_PF_RAMFC, 0x00000110);
/* RAM RO baseadress = $11200 (b1-8), size = 0.5k */
/* (note: so(?) RO base is $00711200, last is $007113ff) */
/*
* (note also: This means(?) the PRAMIN CTX registers are accessible from base $00711400)
*/
setACC(NVACC_PF_RAMRO, 0x00000112);
/* PFIFO size: ch0-15 = 512 bytes, ch16-31 = 124 bytes */
setACC(NVACC_PF_SIZE, 0x0000ffff);
/* cache1 hash instance = $ffff (b0-15) */
setACC(NVACC_PF_CACH1_HASH, 0x0000ffff);
/* disable all PFIFO INTs */
setACC(NVACC_PF_INTEN, 0x00000000);
/* reset all PFIFO INT status bits */
setACC(NVACC_PF_INTSTAT, 0xffffffff);
/* cache0 pull0 engine = acceleration engine (graphics) */
setACC(NVACC_PF_CACH0_PUL1, 0x00000001);
/* cache1 push0 access enabled */
setACC(NVACC_PF_CACH1_PSH0, 0x00000001);
/* cache1 pull0 access enabled */
setACC(NVACC_PF_CACH1_PUL0, 0x00000001);
/* cache1 pull1 engine = acceleration engine (graphics) */
setACC(NVACC_PF_CACH1_PUL1, 0x00000001);
/* enable PFIFO caches reassign */
setACC(NVACC_PF_CACHES, 0x00000001);
/** * PRAMIN ** */
/* RAMHT space (hash-table(?)) */
/* (first set) */
setACC(NVACC_HT_HANDL_00, 0x80000010); /* 32bit handle */
setACC(NVACC_HT_VALUE_00, 0x80011145); /* instance $1145, engine = acc engine, CHID = $00 */
setACC(NVACC_HT_HANDL_01, 0x80000011); /* 32bit handle */
setACC(NVACC_HT_VALUE_01, 0x80011146); /* instance $1146, engine = acc engine, CHID = $00 */
setACC(NVACC_HT_HANDL_02, 0x80000012); /* 32bit handle */
setACC(NVACC_HT_VALUE_02, 0x80011147); /* instance $1147, engine = acc engine, CHID = $00 */
setACC(NVACC_HT_HANDL_03, 0x80000013); /* 32bit handle */
setACC(NVACC_HT_VALUE_03, 0x80011148); /* instance $1148, engine = acc engine, CHID = $00 */
setACC(NVACC_HT_HANDL_04, 0x80000014); /* 32bit handle */
setACC(NVACC_HT_VALUE_04, 0x80011149); /* instance $1149, engine = acc engine, CHID = $00 */
setACC(NVACC_HT_HANDL_05, 0x80000015); /* 32bit handle */
setACC(NVACC_HT_VALUE_05, 0x8001114a); /* instance $114a, engine = acc engine, CHID = $00 */
setACC(NVACC_HT_HANDL_06, 0x80000016); /* 32bit handle */
if (architecture != NV04A) {
setACC(NVACC_HT_VALUE_06, 0x80011150); /* instance $1150, engine = acc engine, CHID = $00 */
} else {
setACC(NVACC_HT_VALUE_06, 0x8001114f); /* instance $114f, engine = acc engine, CHID = $00 */
}
/* (second set) */
setACC(NVACC_HT_HANDL_10, 0x80000000); /* 32bit handle */
setACC(NVACC_HT_VALUE_10, 0x80011142); /* instance $1142, engine = acc engine, CHID = $00 */
setACC(NVACC_HT_HANDL_11, 0x80000001); /* 32bit handle */
setACC(NVACC_HT_VALUE_11, 0x80011143); /* instance $1143, engine = acc engine, CHID = $00 */
setACC(NVACC_HT_HANDL_12, 0x80000002); /* 32bit handle */
setACC(NVACC_HT_VALUE_12, 0x80011144); /* instance $1144, engine = acc engine, CHID = $00 */
setACC(NVACC_HT_HANDL_13, 0x80000003); /* 32bit handle */
setACC(NVACC_HT_VALUE_13, 0x8001114b); /* instance $114b, engine = acc engine, CHID = $00 */
setACC(NVACC_HT_HANDL_14, 0x80000004); /* 32bit handle */
setACC(NVACC_HT_VALUE_14, 0x8001114c); /* instance $114c, engine = acc engine, CHID = $00 */
setACC(NVACC_HT_HANDL_15, 0x80000005); /* 32bit handle */
setACC(NVACC_HT_VALUE_15, 0x8001114d); /* instance $114d, engine = acc engine, CHID = $00 */
setACC(NVACC_HT_HANDL_16, 0x80000006); /* 32bit handle */
setACC(NVACC_HT_VALUE_16, 0x8001114e); /* instance $114e, engine = acc engine, CHID = $00 */
if (architecture != NV04A) {
setACC(NVACC_HT_HANDL_17, 0x80000007); /* 32bit handle */
setACC(NVACC_HT_VALUE_17, 0x8001114f); /* instance $114f, engine = acc engine, CHID = $00 */
}
/* program CTX registers: CTX1 is mostly done later (colorspace dependant) */
/* (setup 'root' set first) */
setACC(NVACC_PR_CTX0_R, 0x00003000); /* NVclass = NVroot, chromakey and userclip enabled */
/* fixme: CTX1_R should reflect RAM amount? (no influence on current used functions) */
setACC(NVACC_PR_CTX1_R, 0x01ffffff); /* cardmemory mask(?) */
setACC(NVACC_PR_CTX2_R, 0x00000002); /* ??? */
setACC(NVACC_PR_CTX3_R, 0x00000002); /* ??? */
/* (setup set '0') */
setACC(NVACC_PR_CTX0_0, 0x01008043); /* NVclass $043, patchcfg ROP_AND, nv10+: little endian */
setACC(NVACC_PR_CTX2_0, 0x00000000); /* DMA0 and DMA1 instance invalid */
setACC(NVACC_PR_CTX3_0, 0x00000000); /* method traps disabled */
/* (setup set '1') */
setACC(NVACC_PR_CTX0_1, 0x01008019); /* NVclass $019, patchcfg ROP_AND, nv10+: little endian */
setACC(NVACC_PR_CTX2_1, 0x00000000); /* DMA0 and DMA1 instance invalid */
setACC(NVACC_PR_CTX3_1, 0x00000000); /* method traps disabled */
/* (setup set '2') */
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