lf240x_a.h

2407的交流电机控制程序

CAP4FIFO		.set 7523h	; Two-level deep Capture FIFO stack 4
CAP5FIFO		.set 7524h	; Two-level deep Capture FIFO stack 5
CAP6FIFO		.set 7525h	; Two-level deep Capture FIFO stack 6
CAP4FBOT		.set 7527h	; Bottom register of Capture FIFO stack 4
CAP5FBOT		.set 7528h	; Bottom register of Capture FIFO stack 5
CAP6FBOT		.set 7529h	; Bottom register of Capture FIFO stack 6
EVBIMRA		.set 752ch	; Group A Interrupt Mask Register
EVBIMRB		.set 752dh	; Group B Interrupt Mask Register
EVBIMRC		.set 752eh	; Group C Interrupt Mask Register
EVBIFRA		.set 752fh	; Group A Interrupt Flag Register
EVBIFRB		.set 7530h	; Group B Interrupt Flag Register
EVBIFRC		.set 7531h	; Group C Interrupt Flag Register

;----------------------------------------------------------------------------
; CAN registers
;----------------------------------------------------------------------------
CANMDER		.set 7100h	; CAN Mailbox Direction/Enable register
CANTCR		       .set 7101h	; CAN Transmission Control register
CANRCR		       .set 7102h	; CAN Recieve Control register
CANMCR		       .set 7103h	; CAN Master Control register
CANBCR2		.set 7104h	; CAN Bit Config register 2
CANBCR1		.set 7105h	; CAN Bit Config register 1
CANESR		       .set 7106h	; CAN Error Status register
CANGSR		       .set 7107h	; CAN Global Status register
CANCEC		       .set 7108h	; CAN Trans and Rcv Err counters
CANIFR		       .set 7109h	; CAN Interrupt Flag Register
CANIMR		       .set 710ah	; CAN Interrupt Mask Register
CANLAM0H		.set 710bh	; CAN Local Acceptance Mask MBX0/1
CANLAM0L		.set 710ch	; CAN Local Acceptance Mask MBX0/1
CANLAM1H		.set 710dh	; CAN Local Acceptance Mask MBX2/3
CANLAM1L		.set 710eh	; CAN Local Acceptance Mask MBX2/3
CANMSGID0L	       .set 7200h	; CAN Message ID for mailbox 0 (lower 16 bits)
CANMSGID0H	       .set 7201h	; CAN Message ID for mailbox 0 (upper 16 bits)
CANMSGCTRL0	       .set 7202h	; CAN RTR and DLC
CANMBX0A		.set 7204h	; CAN 2 of 8 bytes of Mailbox 0
CANMBX0B		.set 7205h	; CAN 2 of 8 bytes of Mailbox 0
CANMBX0C		.set 7206h	; CAN 2 of 8 bytes of Mailbox 0
CANMBX0D		.set 7207h	; CAN 2 of 8 bytes of Mailbox 0
CANMSGID1L	       .set 7208h	; CAN Message ID for mailbox 1 (lower 16 bits)
CANMSGID1H	       .set 7209h	; CAN Message ID for mailbox 1 (upper 16 bits)
CANMSGCTRL1	       .set 720Ah	; CAN RTR and DLC
CANMBX1A		.set 720Ch	; CAN 2 of 8 bytes of Mailbox 1
CANMBX1B		.set 720Dh	; CAN 2 of 8 bytes of Mailbox 1
CANMBX1C		.set 720Eh	; CAN 2 of 8 bytes of Mailbox 1
CANMBX1D		.set 720Fh	; CAN 2 of 8 bytes of Mailbox 1
CANMSGID2L		.set 7210h	; CAN Message ID for mailbox 2 (lower 16 bits)
CANMSGID2H		.set 7211h	; CAN Message ID for mailbox 2 (upper 16 bits)
CANMSGCTRL2		.set 7212h	; CAN RTR and DLC
CANMBX2A		.set 7214h	; CAN 2 of 8 bytes of Mailbox 2
CANMBX2B		.set 7215h	; CAN 2 of 8 bytes of Mailbox 2
CANMBX2C		.set 7216h	; CAN 2 of 8 bytes of Mailbox 2
CANMBX2D		.set 7217h	; CAN 2 of 8 bytes of Mailbox 2
CANMSGID3L		.set 7218h	; CAN Message ID for mailbox 3 (lower 16 bits)
CANMSGID3H		.set 7219h	; CAN Message ID for mailbox 3 (upper 16 bits)
CANMSGCTRL3		.set 721Ah	; CAN RTR and DLC
CANMBX3A		.set 721Ch	; CAN 2 of 8 bytes of Mailbox 3
CANMBX3B		.set 721Dh	; CAN 2 of 8 bytes of Mailbox 3
CANMBX3C		.set 721Eh	; CAN 2 of 8 bytes of Mailbox 3
CANMBX3D		.set 721Fh	; CAN 2 of 8 bytes of Mailbox 3
CANMSGID4L		.set 7220h	; CAN Message ID for mailbox 4 (lower 16 bits)
CANMSGID4H		.set 7221h	; CAN Message ID for mailbox 4 (upper 16 bits)
CANMSGCTRL4		.set 7222h	; CAN RTR and DLC
CANMBX4A		.set 7224h	; CAN 2 of 8 bytes of Mailbox 4
CANMBX4B		.set 7225h	; CAN 2 of 8 bytes of Mailbox 4
CANMBX4C		.set 7226h	; CAN 2 of 8 bytes of Mailbox 4
CANMBX4D		.set 7227h	; CAN 2 of 8 bytes of Mailbox 4
CANMSGID5L		.set 7228h	; CAN Message ID for mailbox 5 (lower 16 bits)
CANMSGID5H		.set 7229h	; CAN Message ID for mailbox 5 (upper 16 bits)
CANMSGCTRL5		.set 722Ah	; CAN RTR and DLC
CANMBX5A		.set 722Ch	; CAN 2 of 8 bytes of Mailbox 5
CANMBX5B		.set 722Dh	; CAN 2 of 8 bytes of Mailbox 5
CANMBX5C		.set 722Eh	; CAN 2 of 8 bytes of Mailbox 5
CANMBX5D		.set 722Fh	; CAN 2 of 8 bytes of Mailbox 5

;----------------------------------------------------------------------------
; I/O space mapped registers
;----------------------------------------------------------------------------

WSGR			.set 0FFFFh	; Wait State Generator Control register
FCMR			.set 0FF0Fh	; Flash control mode register

;----------------------------------------------------------------------------
; Constant Defines
;----------------------------------------------------------------------------
B0DS_SADDR	.set 00200h	; Block B0 Start Address in Data Space (CNF=0)
B0DS_EADDR	.set 002FFh	; Block B0 End Address in Data Space (CNF=0)
B1_SADDR	.set 00300h	; Block B1 Start Address
B1_EADDR	.set 003FFh	; Block B1 End Address
B2_SADDR	.set 00060h	; Block B2 Start Address
B2_EADDR	.set 0007Fh	; Block B2 End Address
IDS_SADDR	.set 00800h	; Internal DARAM Start Address in Data Space (DON=1)
IDS_EADDR	.set 00FFFh	; Internal DARAM End Address in Data Space (DON=1)
XDS_SADDR	.set 08000h	; External Data Space Start Address
XDS_EADDR	.set 0FFFFh	; External Data Space End Address

B0PS_SADDR	.set 0FE00h	; Block B0 Start Address in Program Space (CNF=1)
B0PS_EADDR	.set 0FEFFh	; Block B0 End Address in Program Space (CNF=1)
IPS_SADDR	.set 08000h	; Internal DARAM Start Address in Program Space (PON=1)
IPS_EADDR	.set 087FFh	; Internal DARAM End Address in Program Space (PON=1)
XPS_SADDR	.set 08000h	; External Program Space Start Address
XPS_EADDR	.set 0FEFFh	; External Program Space End Address
XIO_SADDR	.set 08000h	; External I/O Space Start Address
XIO_EADDR	.set 0FEFFh	; External I/O Space End Address

;----------------------------------------------------------------------------
; Bit Codes for Test Bit Instruction (BIT)
;----------------------------------------------------------------------------
BIT15		.set 0000h	; Bit Code for 15
BIT14		.set 0001h	; Bit Code for 14
BIT13		.set 0002h	; Bit Code for 13
BIT12		.set 0003h	; Bit Code for 12
BIT11		.set 0004h	; Bit Code for 11
BIT10		.set 0005h	; Bit Code for 10
BIT9		.set 0006h	; Bit Code for 9
BIT8		.set 0007h	; Bit Code for 8
BIT7		.set 0008h	; Bit Code for 7
BIT6		.set 0009h	; Bit Code for 6
BIT5		.set 000Ah	; Bit Code for 5
BIT4		.set 000Bh	; Bit Code for 4
BIT3		.set 000Ch	; Bit Code for 3
BIT2		.set 000Dh	; Bit Code for 2
BIT1		.set 000Eh	; Bit Code for 1
BIT0		.set 000Fh	; Bit Code for 0
;----------------------------------------------------------------------------
; Bit masks to reset a bit with AND
;----------------------------------------------------------------------------
RSTB15		.set 7FFFh	; Bit Mask for 15
RSTB14		.set 0BFFFh	; Bit Mask for 14
RSTB13		.set 0DFFFh	; Bit Mask for 13
RSTB12		.set 0EFFFh	; Bit Mask for 12
RSTB11		.set 0F7FFh	; Bit Mask for 11
RSTB10		.set 0FBFFh	; Bit Mask for 10
RSTB9		.set 0FDFFh	; Bit Mask for 9
RSTB8		.set 0FEFFh	; Bit Mask for 8
RSTB7		.set 0FF7Fh	; Bit Mask for 7
RSTB6		.set 0FFBFh	; Bit Mask for 6
RSTB5		.set 0FFDFh	; Bit Mask for 5
RSTB4		.set 0FFEFh	; Bit Mask for 4
RSTB3		.set 0FFF7h	; Bit Mask for 3
RSTB2		.set 0FFFBh	; Bit Mask for 2
RSTB1		.set 0FFFDh	; Bit Mask for 1
RSTB0		.set 0FFFEh	; Bit Mask for 0
;----------------------------------------------------------------------------
; Bit masks to set a bit with OR
;----------------------------------------------------------------------------
SETB15		.set 8000h	; Bit Mask for 15
SETB14		.set 4000h	; Bit Mask for 14
SETB13		.set 2000h	; Bit Mask for 13
SETB12		.set 1000h	; Bit Mask for 12
SETB11		.set 0800h	; Bit Mask for 11
SETB10		.set 0400h	; Bit Mask for 10
SETB9		.set 0200h	; Bit Mask for 9
SETB8		.set 0100h	; Bit Mask for 8
SETB7		.set 0080h	; Bit Mask for 7
SETB6		.set 0040h	; Bit Mask for 6
SETB5		.set 0020h	; Bit Mask for 5
SETB4		.set 0010h	; Bit Mask for 4
SETB3		.set 0008h	; Bit Mask for 3
SETB2		.set 0004h	; Bit Mask for 2
SETB1		.set 0002h	; Bit Mask for 1
SETB0		.set 0001h	; Bit Mask for 0

;----------------------------------------------------------------------------
; Data Page Pointer Definitions
;----------------------------------------------------------------------------
DP_EV		.set 0E8h	; Data Page for EV (7400h-7480h)
DP_PF1		.set 0E0h	; Data Page for Peripheral File 1 (7000h-7080h)
DP_PF2		.set 0E1h	; Data Page for Peripheral File 2 (7080h-7100h)
DP_CAN1	.set 0E2h	; Data Page for CAN Global Registers (7100h-7180h)
DP_CAN2	.set 0E4h	; Data Page for CAN Mailboxes Registers (7200h-7280h)
;----------------------------------------------------------------------------