📄 lf240x_a.h
字号:
;****************************************************************************
; File Name : LF240x_a.h
; Project : IM V/f control on ACPM750 AC Power Module Kit with
; TMS320LF2407 DSP controller
;============================================================================
; Target Sys : MSK2407 DSP board + ACPM750 v3.2 power module
; Description : 'LF2407 Header file with all Peripheral Register declarations
; and other useful defines.
; Originator/s: Technosoft Ltd.
; Status : OK
;****************************************************************************
; Copyright ?2000 Technosoft
;============================================================================
; On Chip Periperal Register Definitions (DATA SPACE)
;----------------------------------------------------------------------------
; 240x CPU core registers
;----------------------------------------------------------------------------
IMR .set 0004h ; Interrupt Mask Register
IFR .set 0006h ; Interrupt Flag Register
;----------------------------------------------------------------------------
; System configuration and interrupt registers
;----------------------------------------------------------------------------
SCSR1 .set 7018h ; System Control & Status register. 1
SCSR2 .set 7019h ; System Control & Status register. 2
DIN .set 701Ch ; Device Identification Number register.
PIVR .set 701Eh ; Peripheral Interrupt Vector register.
PIRQR0 .set 7010h ; Peripheral Interrupt Request register 0
PIRQR1 .set 7011h ; Peripheral Interrupt Request register 1
PIRQR2 .set 7012h ; Peripheral Interrupt Request register 2
PIACKR0 .set 7014h ; Peripheral Interrupt Acknowledge register 0
PIACKR1 .set 7015h ; Peripheral Interrupt Acknowledge register 1
PIACKR2 .set 7016h ; Peripheral Interrupt Acknowledge register 2
;----------------------------------------------------------------------------
; External interrupt configuration registers
;----------------------------------------------------------------------------
XINT1CR .set 7070h ; XInt1 Control Register
XINT2CR .set 7071h ; XInt2 Control Register
;----------------------------------------------------------------------------
; Digital I/O registers
;----------------------------------------------------------------------------
MCRA .set 07090h ; I/O Mux. Control Register A
MCRB .set 07092h ; I/O Mux. Control Register B
MCRC .set 7094h ; I/O Mux Control Register C
PADATDIR .set 07098h ; I/O port A Data & Direction Register
PBDATDIR .set 0709Ah ; I/O port B Data & Direction Register
PCDATDIR .set 0709Ch ; I/O port C Data & Direction Register
PDDATDIR .set 0709Eh ; I/O port D Data & Direction reg.
PEDATDIR .set 7095h ; I/O port E Data & Direction register
PFDATDIR .set 7096h ; I/O port F Data & Direction register
;----------------------------------------------------------------------------
; Watchdog (WD) registers
;----------------------------------------------------------------------------
WDCNTR .set 07023h ; WD Counter Register
WDKEY .set 07025h ; WD Reset Key Register
WDCR .set 07029h ; WD Control Register
;----------------------------------------------------------------------------
; ADC registers
;----------------------------------------------------------------------------
ADCTRL1 .set 70A0h ; ADC Control register 1
ADCTRL2 .set 70A1h ; ADC Control register 2
MAX_CONV .set 70A2h ; Maximum conversion channels register
CHSELSEQ1 .set 70A3h ; Channel select Sequencing control register 1
CHSELSEQ2 .set 70A4h ; Channel select Sequencing control register 2
CHSELSEQ3 .set 70A5h ; Channel select Sequencing control register 3
CHSELSEQ4 .set 70A6h ; Channel select Sequencing control register 4
AUTO_SEQ_SR .set 70A7h ; Auto sequence status register
RESULT0 .set 70A8h ; Conversion result buffer register 0
RESULT1 .set 70A9h ; Conversion result buffer register 1
RESULT2 .set 70Aah ; Conversion result buffer register 2
RESULT3 .set 70Abh ; Conversion result buffer register 3
RESULT4 .set 70Ach ; Conversion result buffer register 4
RESULT5 .set 70Adh ; Conversion result buffer register 5
RESULT6 .set 70Aeh ; Conversion result buffer register 6
RESULT7 .set 70Afh ; Conversion result buffer register 7
RESULT8 .set 70B0h ; Conversion result buffer register 8
RESULT9 .set 70B1h ; Conversion result buffer register 9
RESULT10 .set 70B2h ; Conversion result buffer register 10
RESULT11 .set 70B3h ; Conversion result buffer register 11
RESULT12 .set 70B4h ; Conversion result buffer register 12
RESULT13 .set 70B5h ; Conversion result buffer register 13
RESULT14 .set 70B6h ; Conversion result buffer register 14
RESULT15 .set 70B7h ; Conversion result buffer register 15
CALIBRATION .set 70B8h ; Calib result, used to correct subsequent conversions
;----------------------------------------------------------------------------
; SPI registers
;----------------------------------------------------------------------------
SPICCR .set 07040h ; SPI Config Control Register
SPICTL .set 07041h ; SPI Operation Control Register
SPISTS .set 07042h ; SPI Status Register
SPIBRR .set 07044h ; SPI Baud Rate Control Register
SPIRXEMU .set 07046h ; SPI Emulation Buffer Register
SPIRXBUF .set 07047h ; SPI Serial receive buffer reg
SPITXBUF .set 07048h ; SPI Serial transmit buffer reg
SPIDAT .set 07049h ; SPI Serial Data Register
SPIPRI .set 0704Fh ; SPI Priority Control Register
;----------------------------------------------------------------------------
; SCI registers
;----------------------------------------------------------------------------
SCICCR .set 07050h ; SCI Communication Control Reg
SCICTL1 .set 07051h ; SCI Control Register 1
SCIHBAUD .set 07052h ; SCI Baud Rate High
SCILBAUD .set 07053h ; SCI Baud Rate Low
SCICTL2 .set 07054h ; SCI Control Register 2
SCIRXST .set 07055h ; SCI Receive Status Register
SCIRXEMU .set 07056h ; SCI EMU Data Buffer
SCIRXBUF .set 07057h ; SCI Receive Data Buffer
SCITXBUF .set 07059h ; SCI Transmit Data Buffer
SCIPRI .set 0705Fh ; SCI Priority Control Register
;----------------------------------------------------------------------------
; Event Manager A (EVA) registers
;----------------------------------------------------------------------------
GPTCONA .set 7400h ; General Timer Controls
T1CNT .set 7401h ; T1 Counter Register
T1CMPR .set 7402h ; T1 Compare Register
T1PR .set 7403h ; T1 Period Register
T1CON .set 7404h ; T1 Control Register
T2CNT .set 7405h ; T2 Counter Register
T2CMPR .set 7406h ; T2 Compare Register
T2PR .set 7407h ; T2 Period Register
T2CON .set 7408h ; T2 Control Register
COMCONA .set 7411h ; Compare Unit Control
ACTRA .set 7413h ; Compare Unit Output Action Control
DBTCONA .set 7415h ; Dead Band Timer Control
CMPR1 .set 7417h ; Compare Channel 1 Threshold
CMPR2 .set 7418h ; Compare Channel 2 Threshold
CMPR3 .set 7419h ; Compare Channel 3 Threshold
CAPCONA .set 7420h ; Capture Unit Control
CAPFIFOA .set 7422h ; Capture FIFO Status Register
CAP1FIFO .set 7423h ; Two-level deep Capture FIFO stack 1
CAP2FIFO .set 7424h ; Two-level deep Capture FIFO stack 2
CAP3FIFO .set 7425h ; Two-level deep Capture FIFO stack 3
CAP1FBOT .set 7427h ; Bottom register of Capture FIFO stack 1
CAP2FBOT .set 7428h ; Bottom register of Capture FIFO stack 2
CAP3FBOT .set 7429h ; Bottom register of Capture FIFO stack 3
EVAIMRA .set 742ch ; Group A Interrupt Mask Register
EVAIMRB .set 742dh ; Group B Interrupt Mask Register
EVAIMRC .set 742eh ; Group C Interrupt Mask Register
EVAIFRA .set 742fh ; Group A Interrupt Flag Register
EVAIFRB .set 7430h ; Group B Interrupt Flag Register
EVAIFRC .set 7431h ; Group C Interrupt Flag Register
;----------------------------------------------------------------------------
; Event Manager B (EVB) registers
;----------------------------------------------------------------------------
GPTCONB .set 7500h ; General Timer Controls
T3CNT .set 7501h ; T3 Counter Register
T3CMPR .set 7502h ; T3 Compare Register
T3PR .set 7503h ; T3 Period Register
T3CON .set 7504h ; T3 Control Register
T4CNT .set 7505h ; T4 Counter Register
T4CMPR .set 7506h ; T4 Compare Register
T4PR .set 7507h ; T4 Period Register
T4CON .set 7508h ; T4 Control Register
COMCONB .set 7511h ; Compare Unit Control
ACTRB .set 7513h ; Compare Unit Output Action Control
DBTCONB .set 7515h ; Dead Band Timer Control
CMPR4 .set 7517h ; Compare Channel 4 Threshold
CMPR5 .set 7518h ; Compare Channel 5 Threshold
CMPR6 .set 7519h ; Compare Channel 6 Threshold
CAPCONB .set 7520h ; Capture Unit Control
CAPFIFOB .set 7522h ; Capture FIFO Status Register
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -