sl811hs_reg.h

ucusb 关于sl811驱动移植源码

/*
*********************************************************************************************************
*                                              Micrium, Inc.
*                                          949 Crestview Circle
*                                         Weston,  FL 33327-1848
*
*                                              uC/USB-Bulk
*
*                                 (c) Copyright 2003 - 2004, Micrium, Inc.
*                                           All rights reserved.
*
*********************************************************************************************************

---------------------------------------------------------------------------------------------------------
File    : SL811HS_reg.h
Purpose : #defines for register addresses and bit masks for Cypress SL811HS USB Controller.  This 
          file also defines macros for accessing the registers using the IP associated with the 
          SL811HS on the Microtronix Cyclone Development Board.
--------  END-OF-HEADER  --------------------------------------------------------------------------------
*/

/*
*********************************************************************************************************
*                                         Endpoint Registers
*********************************************************************************************************
*/

#define ENDPOINT0A_CTRL                     0x00
#define ENDPOINT0A_BASE                     0x01
#define ENDPOINT0A_LEN                      0x02
#define ENDPOINT0A_PKT                      0x03
#define ENDPOINT0A_CNT                      0x04

#define ENDPOINT1A_CTRL                     0x10
#define ENDPOINT1A_BASE                     0x11
#define ENDPOINT1A_LEN                      0x12
#define ENDPOINT1A_PKT                      0x13
#define ENDPOINT1A_CNT                      0x14

#define ENDPOINT2A_CTRL                     0x20
#define ENDPOINT2A_BASE                     0x21
#define ENDPOINT2A_LEN                      0x22
#define ENDPOINT2A_PKT                      0x23
#define ENDPOINT2A_CNT                      0x24

/*
*********************************************************************************************************
*                                     Endpoint Register Bit Masks
*********************************************************************************************************
*/

#define ENDPOINT_CTRL_ARM                   0x01
#define ENDPOINT_CTRL_ENABLE                0x02
#define ENDPOINT_CTRL_DIRECTION             0x04
#define ENDPOINT_CTRL_NEXTSET               0x08
#define ENDPOINT_CTRL_ISO                   0x10
#define ENDPOINT_CTRL_STALL                 0x20
#define ENDPOINT_CTRL_SEQUENCE              0x40

#define ENDPOINT_PKT_ACK                    0x01
#define ENDPOINT_PKT_ERROR                  0x02
#define ENDPOINT_PKT_TIMEOUT                0x04
#define ENDPOINT_PKT_SEQUENCE               0x08
#define ENDPOINT_PKT_SETUP                  0x10
#define ENDPOINT_PKT_OVERFLOW               0x20
#define ENDPOINT_PKT_NAK                    0x40
#define ENDPOINT_PKT_STALL                  0x80

/*
*********************************************************************************************************
*                                         Control Registers
*********************************************************************************************************
*/

#define CTRL_REG                            0x05
#define INT_ENABLE_REG                      0x06
#define ADDR_REG                            0x07
#define INT_STATUS_REG                      0x0D
#define CURRENT_DATA_SET_REG                0x0E
#define CTRL_2_REG                          0x0F
#define SOF_LOW_BYTE_REG                    0x15
#define SOF_HIGH_BYTE_REG                   0x16
#define DMA_TOTAL_CNT_LOW_BYTE_REG          0x35
#define DMA_TOTAL_CNT_HIGH_BYTE_REG         0x36

#define CTRL_2_MASTER                       0x80

/*
*********************************************************************************************************
*                                        Control Register Bit Masks
*********************************************************************************************************
*/

#define CTRL_USB_ENABLE                     0x01
#define CTRL_DMA_ENABLE                     0x02
#define CTRL_DMA_DIRECTION                  0x04
#define CTRL_JK0                            0x08
#define CTRL_JK1                            0x10
#define CTRL_SPSEL                          0x20
#define CTRL_STBYD                          0x40

#define CTRL_2_SLAVE                        0x00

#define INT_ENABLE_ENDPOINT0                0x01
#define INT_ENABLE_ENDPOINT1                0x02
#define INT_ENABLE_ENDPOINT2                0x04
#define INT_ENABLE_ENDPOINT3                0x08
#define INT_ENABLE_DMA                      0x10
#define INT_ENABLE_SOF                      0x20
#define INT_ENABLE_USB_RESET                0x40
#define INT_ENABLE_DMA_STATUS               0x80

#define INT_STATUS_ENDPOINT0                0x01
#define INT_STATUS_ENDPOINT1                0x02
#define INT_STATUS_ENDPOINT2                0x04
#define INT_STATUS_ENDPOINT3                0x08
#define INT_STATUS_DMA                      0x10
#define INT_STATUS_SOF                      0x20
#define INT_STATUS_USB_RESET                0x40
#define INT_STATUS_DMA_STATUS               0x80
#define INT_STATUS_CLEAR_ALL                0xFF

#define CURRENT_DATA_SET_ENDPOINT0          0x01
#define CURRENT_DATA_SET_ENDPOINT1          0x02
#define CURRENT_DATA_SET_ENDPOINT2          0x04
#define CURRENT_DATA_SET_ENDPOINT3          0x08