📄 int_5307.s
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;/* HISTORY */;/* */;/* NAME DATE REMARKS */;/* */;/* B. Sellew 04-28-1998 Created and verified version 1.0 */;/* */;/*************************************************************************/ XDEF _INT_Initialize_INT_Initialize: XDEF _main_main:;VOID INT_Initialize(void);{;; /* Lockout interrupts during initialization. */; MOVE.W #$2700,SR ; Lockout interrupts;; /* Initialize chip selects */; MOVE.B #$FE,D0 MOVE.B D0,($10000098) ; CSAR2 MOVE.L #$00000001,D0 MOVE.L D0,($1000009C) ; CSMR2 MOVE.W #$0040,D0 MOVE.W D0,($100000A2) ; CSCR2 MOVE.W #$0015,D0 MOVE.W D0,($100000AA) ; CSMR3 MOVE.W #$0080,D0 MOVE.W D0,($100000AE) ; CSCR3 MOVE.W #$001F,D0 MOVE.W D0,($100000B6) ; CSMR4 MOVE.W #$0040,D0 MOVE.W D0,($100000BA) ; CSCR4 MOVE.L #$00000000,D0 MOVE.L D0,($10000090) ; CSMR1 MOVE.W #$0000,D0 MOVE.W D0,($100000C2) ; CSMR5 MOVE.W #$0000,D0 MOVE.W D0,($100000CE) ; CSMR6 MOVE.W #$0000,D0 MOVE.W D0,($100000DA) ; CSMR7 MOVE.W #$FFE0,D0 MOVE.W D0,($10000080) ; CSAR0 MOVE.W #$0D80,D0 MOVE.W D0,($1000008A) ; CSCR0 MOVE.L #$000F0001,D0 MOVE.L D0,($10000084) ; CSMR0 move.l #0x10000000,-(sp) jsr _mcf5307_sim_init jsr _mcf5307_timer_init jsr _mcf5307_pport_init jsr _mcf5307_mbus_init jsr _mcf5307_dma_init jsr _mcf5307_cs_init jsr _mcf5307_uart_init ;; /* Setup the vectors loaded flag to indicate to other routines in the ; system whether or not all of the default vectors have been loaded. ; If INT_Loaded_Flag is 1, all of the default vectors have been loaded.; Otherwise, if INT_Loaded_Flag is 0, registering an LISR cause the; default vector to be loaded. */; INT_Loaded_Flag = 1;; MOVE.L #1,D0 MOVE.L D0,_INT_Loaded_Flag;; /* Reset the VBR to point to address zero. */; MOVE.L A7,D1 MOVE.L #0,D0 MOVEA.L D0,A7 MOVEC.L A7,VBR MOVEA.L D1,A7; ***** BEGIN board specific code for the MCF5307 evaluation board *****;; /* Set up Timer 1 for a 10ms periodic tick that generates a Level 5; autovector. */; MOVE.L #ICR1_CFG,D0 ; Pick up configuration value for ICR1 MOVE.B D0,(MBAR_ADDR+ICR1) ; Setup Timer 1 interrupt for lev 5, pri 0 MOVE.L #TRR1_LOAD,D0 ; Pick up compare value MOVE.W D0,(MBAR_ADDR+TRR1) ; Load into TRR1, val = (25MHz / 16) / 100 MOVE.L #TMR1_CFG,D0 ; Pick up configuration value for TMR1 MOVE.W D0,(MBAR_ADDR+TMR1) ; Setup Timer 1 ; Prescaler = 0 ; Enable reference interrupt ; Restart timer after reference reached ; System clock / 16 ; Enable timer MOVE.L (MBAR_ADDR+IMR),D0 ; Get current interrupt lockout status ANDI.L #IMR_MASK,D0 ; Clear Timer 1 bit MOVE.L D0,(MBAR_ADDR+IMR) ; Enable Timer 1 interrupt MOVEA.L #0,A0 ;level 5 Pointer to the vector table MOVE.L #0x1d,D0 ; vector number is #0x1d ,offset is 0x78 LSL.L #2,D0 ; Adjust for the vector size ADDA.L D0,A0 ; Add in offset to vector base MOVE.L #_INT_Timer_Interrupt, D0 MOVE.L D0,(A0) MOVEA.L #0,A0 ;UART level 1 Pointer to the vector table MOVE.L #0x19,D0 ; vector number is #0x19 ,offset is 0x64 LSL.L #2,D0 ; Adjust for the vector size ADDA.L D0,A0 ; Add in offset to vector base MOVE.L #_INT_Level_1_Auto,D0 ;use stardard routing #_INT_Uart1_Interrupt, D0 MOVE.L D0,(A0) MOVEA.L #0,A0 ;NIC leval 2 Pointer to the vector table MOVE.L #0x1a,D0 ; vector number is #0x1c ,offset is 0x6c LSL.L #2,D0 ; Adjust for the vector size ADDA.L D0,A0 ; Add in offset to vector base MOVE.L #_INT__Interrupt_Level2, D0 ;#_INT_Level_2_Auto, D0 ; stardard use LISR _INT__Interrupt_Level2, D0 MOVE.L D0,(A0) MOVEA.L #0,A0 ;level 3 Pointer to the vector table MOVE.L #0x1b,D0 ; vector number is #0x1b ,offset is 0x6c LSL.L #2,D0 ; Adjust for the vector size ADDA.L D0,A0 ; Add in offset to vector base MOVE.L #_INT_Mbus_Interrupt, D0 MOVE.L D0,(A0) JSR _cpu_cache_disable ;//in cache.s JSR _EnableCache ; ***** END board specific code for the MCF5307 evaluation board *****;; /* Save the current value of the system stack. */; CLR.L -(A7) ; Place a NULL on the system stack MOVE.L A7,_TCD_System_Stack ; Save system stack pointer; ; /* Define the global data structures that need to be initialized by this; routine. These structures are used to define the system timer ; management HISR. */; TMD_HISR_Stack_Ptr = _sys_memory;; TMD_HISR_Stack_Size = HISR_STACK;; TMD_HISR_Priority = 0;; MOVE.L #HISR_STACK,D0 ; pick up size of HISR stack MOVE.L D0,_TMD_HISR_Stack_Size ; store in variable CLR.L D0 ; get a 0 MOVE.L D0,_TMD_HISR_Priority ; store priority = 0 MOVE.L #_sys_memory,D0 ; get address of sys_memory section MOVE.L D0,_TMD_HISR_Stack_Ptr ; set up as HISR stack ADD.L #HISR_STACK,D0 ; move available mem pointer up;; /* Invalidate, then enable the cache */;; MOVE.L #CACHE_INV,D1 ; pick up Invalidate All command; MOVEC D1,CACR ; invalidate all cache lines; MOVE.L #CACHE_EN,D1 ; pick up Enable command; MOVEC D1,CACR ; enable the cache, but default to ; cache-inhibited access for all ; memory not defined in ACRs; MOVE.L #ACR0_CFG,D1 ; pick up ACR0 configuration; MOVEC D1,ACR0 ; enable cache for DRAM accesses ;;; /* Call INC_Initialize with a pointer to the first available memory ; address after the compiler's global data. This memory may be used; by the application. */; INC_Initialize(first_available_address);; MOVE.L D0,-(A7) JSR _INC_Initialize;};;;/*************************************************************************/;/* */;/* FUNCTION */;/* */;/* INT_Vectors_Loaded */;/* */;/* DESCRIPTION */;/* */;/* This function returns the flag that indicates whether or not */;/* all the default vectors have been loaded. If it is false, */;/* each LISR register also loads the ISR shell into the actual */;/* vector table. */;/* */;/* AUTHOR */;/* */;/* Barry Sellew, Accelerated Technology, Inc. */;/* */;/* CALLED BY */;/* */;/* TCC_Register_LISR Register LISR for vector */;/* */;/* CALLS */;/* */;/* None */;/* */;/* INPUTS */;/* */;/* None */;/* */;/* OUTPUTS */;/* */;/* None */;/* */;/* HISTORY */;/* */;/* NAME DATE REMARKS */;/* */;/* B. Sellew 04-28-1998 Created and verified version 1.0 */;/* */;/*************************************************************************/ XDEF _INT_Vectors_Loaded⌨️ 快捷键说明
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