📄 int_5307.s
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;/*************************************************************************/;/* */;/* Copyright (c) 1993-1999 Accelerated Technology, Inc. */;/* */;/* PROPRIETARY RIGHTS of Accelerated Technology are involved in the */;/* subject matter of this material. All manufacturing, reproduction, */;/* use, and sales rights pertaining to this subject matter are governed */;/* by the license agreement. The recipient of this software implicitly */;/* accepts the terms of the license. */;/* */;/*************************************************************************/;;/*************************************************************************/;/* */;/* FILE NAME VERSION */;/* */;/* int_5307.s PLUS/MCF5307/D 1.11.5 */;/* */;/* COMPONENT */;/* */;/* IN - Initialization */;/* */;/* DESCRIPTION */;/* */;/* This file contains the target processor dependent initialization */;/* routines and data. */;/* */;/* AUTHOR */;/* */;/* Barry Sellew, Accelerated Technology, Inc. */;/* */;/* DATA STRUCTURES */;/* */;/* INT_Vectors Interrupt vector table */;/* */;/* FUNCTIONS */;/* */;/* INT_Initialize Target initialization */;/* INT_Vectors_Loaded Returns a NU_TRUE if all the */;/* default vectors are loaded */;/* INT_Setup_Vector Sets up an actual vector */;/* */;/* DEPENDENCIES */;/* */;/* nucleus.h System constants */;/* */;/* HISTORY */;/* */;/* NAME DATE REMARKS */;/* */;/* B. Sellew 04-28-1998 Created and verified version 1.0 */;/* B. Sellew 08-25-1998 Created version 1.1 */;/* B. Sellew 09-17-1998 Created version 1.2 */;/* K. Pontzloff 10-30-1998 Created version 1.3 */;/* M. Winter 06-18-1999 Updated port to enable cache */;/* Release 1.11.5 */;/* */;/*************************************************************************/;#define NU_SOURCE_FILE;;#include "nucleus.h" /* System constants */;;;/* Define the global system stack variable. This is setup by the ; initialization routine. */;;extern VOID *TCD_System_Stack;; XREF _TCD_System_Stack;;;/* Define the global data structures that need to be initialized by this; routine. These structures are used to define the system timer management; HISR. */; ;extern VOID *TMD_HISR_Stack_Ptr;;extern UNSIGNED TMD_HISR_Stack_Size;;extern INT TMD_HISR_Priority;; XREF _TMD_HISR_Stack_Ptr XREF _TMD_HISR_Stack_Size XREF _TMD_HISR_Priority XREF START XREF STKTOP;;;/* Define extern function references. */;;VOID INC_Initialize(VOID *first_available_memory);;VOID TCT_Interrupt_Context_Save(VOID);;VOID TCT_Interrupt_Context_Restore(VOID);;VOID TCC_Dispatch_LISR(INT vector_number);;VOID TMT_Timer_Interrupt(VOID);; XREF _INC_Initialize XREF _TCT_Interrupt_Context_Save XREF _TCT_Interrupt_Context_Restore XREF _TCC_Dispatch_LISR XREF _TMT_Timer_Interrupt;;;/* Define the initialization flag that indicates whether or not all of the; default vectors have been loaded during initialization. */;;INT INT_Loaded_Flag;; SECTION .bss XDEF _INT_Loaded_Flag_INT_Loaded_Flag: DS.B 4;;/* Define the sizes for the system stack and the timer management stack. */;HISR_STACK EQU 500 ; Size of Timer HISR stack;;/* Define addresses, offsets, and values for programming Timer 1;MBAR_ADDR EQU $10000000 ; Base address of all internal regs; ***** BEGIN board specific code for the MCF5307 evaluation board *****TMR1 EQU $140 ; Offset of Timer 1 Mode RegisterTRR1 EQU $144 ; Offset of Timer 1 Reference RegTER1 EQU $151 ; Offset of Timer 1 Event RegisterICR1 EQU $4d ; Offset of Timer 1 Int Control Reg; ***** END board specific code for the MCF5307 evaluation board *****IMR EQU $44 ; Offset of Interrupt Mask RegisterCACR EQU $002 ; Cache Control Register; ***** BEGIN board specific code for the MCF5307 evaluation board *****TMR1_CFG EQU $1d ; Value to configure Timer 1TRR1_LOAD EQU $6ddd ; Value to be compared to counterTER1_CLEAR EQU $ff ; Value to clear timer interruptICR1_CFG EQU $94 ; Value to configure Timer 1 intIMR_MASK EQU $fffffdff ; Mask to enable Timer 1 interrupt; ***** END board specific code for the MCF5307 evaluation board *****CACHE_INV EQU $01000000 ; Value to invalidate entire cacheCACHE_EN EQU $80000300 ; Value to enable cache, defaulting ; to cache-inhibit for all memory ; not defined in an ACR registerACR0_CFG EQU $0001C000 ; Value to enable cache for DRAM;;/* Define the sections that allocate space for the system stack and possibly; the heap. Also, define a section that is used to identify where the ; available system memory starts. */; XREF _sys_memory;;;/* Define the interrupt vector table for the 5307. Note that this; vector table (or a copy of it) resides at address 0. In situations; where co-existence with a target monitor is required, this vector table; is typically not completely loaded. The template interrupt vectors are; defined at the bottom of this file. */; SECTION .vectors XDEF _INT_Vectors_INT_Vectors: DC.L STKTOP-4 ; Initial stack value 0 DC.L START ; System entry location 1 DC.L _INT_Bus_Error ; Bus Error 2 DC.L _INT_Address_Error ; Address Error 3 DC.L _INT_Illegal_Instruction ; Illegal Instruction 4 DC.L _INT_Zero_Divide ; Divide by zero 5 DC.L _INT_Chk_Chk2 ; CHK and CHK2 instructions 6 DC.L _INT_TrapV ; TRAPV instruction 7 DC.L _INT_Privilege ; Privilege violation 8 DC.L _INT_Trace ; Trace 9 DC.L _INT_Emul_A ; Emulate A 10 DC.L _INT_Emul_B ; Emulate B 11 DC.L _INT_Hdw_Breakpoint ; Hardware breakpoint 12 DC.L _INT_Coprocessor_Violate ; Coprocessor violation 13 DC.L _INT_Format_Error ; Format error 14 DC.L _INT_Uninitialized_Int ; Uninitialized interrupt 15 DC.L _INT_Reserved_0 ; Reserved 0 16 DC.L _INT_Reserved_1 ; Reserved 1 17 DC.L _INT_Reserved_2 ; Reserved 2 18 DC.L _INT_Reserved_3 ; Reserved 3 19 DC.L _INT_Reserved_4 ; Reserved 4 20 DC.L _INT_Reserved_5 ; Reserved 5 21 DC.L _INT_Reserved_6 ; Reserved 6 22 DC.L _INT_Reserved_7 ; Reserved 7 23 DC.L _INT_Spurious ; Spurious interrupt 24 DC.L _INT_Level_1_Auto ; Level 1 Autovector 25 DC.L _INT_Level_2_Auto ; Level 2 Autovector 26 DC.L _INT_Level_3_Auto ; Level 3 Autovector 27 DC.L _INT_Level_4_Auto ; Level 4 Autovector 28; DC.L _INT_Level_5_Auto ; Level 5 Autovector 29; Steal Level 5 autovector for Timer 1 interrupt DC.L _INT_Timer_Interrupt ; Timer interrupt function DC.L _INT_Level_6_Auto ; Level 6 Autovector 30 DC.L _INT_Level_7_Auto ; Level 7 Autovector 31 DC.L _INT_Trap_0 ; Trap 0 32 DC.L _INT_Trap_1 ; Trap 1 33 DC.L _INT_Trap_2 ; Trap 2 34 DC.L _INT_Trap_3 ; Trap 3 35 DC.L _INT_Trap_4 ; Trap 4 36 DC.L _INT_Trap_5 ; Trap 5 37 DC.L _INT_Trap_6 ; Trap 6 38 DC.L _INT_Trap_7 ; Trap 7 39 DC.L _INT_Trap_8 ; Trap 8 40 DC.L _INT_Trap_9 ; Trap 9 41 DC.L _INT_Trap_10 ; Trap 10 42 DC.L _INT_Trap_11 ; Trap 11 43 DC.L _INT_Trap_12 ; Trap 12 44 DC.L _INT_Trap_13 ; Trap 13 45 DC.L _INT_Trap_14 ; Trap 14 46 DC.L _INT_Trap_15 ; Trap 15 47 DC.L _INT_Cop_Reserved_0 ; Coprocessor Reserved 0 48 DC.L _INT_Cop_Reserved_1 ; Coprocessor Reserved 1 49 DC.L _INT_Cop_Reserved_2 ; Coprocessor Reserved 2 50 DC.L _INT_Cop_Reserved_3 ; Coprocessor Reserved 3 51 DC.L _INT_Cop_Reserved_4 ; Coprocessor Reserved 4 52 DC.L _INT_Cop_Reserved_5 ; Coprocessor Reserved 5 53 DC.L _INT_Cop_Reserved_6 ; Coprocessor Reserved 6 54 DC.L _INT_Cop_Reserved_7 ; Coprocessor Reserved 7 55 DC.L _INT_Cop_Reserved_8 ; Coprocessor Reserved 8 56 DC.L _INT_Cop_Reserved_9 ; Coprocessor Reserved 9 57 DC.L _INT_Cop_Reserved_10 ; Coprocessor Reserved 10 58 DC.L _INT_Reserved_8 ; Reserved 8 59 DC.L _INT_Reserved_9 ; Reserved 9 60 DC.L _INT_Reserved_10 ; Reserved 10 61 DC.L _INT_Reserved_11 ; Reserved 11 62 DC.L _INT_Reserved_12 ; Reserved 12 63 DC.L _INT_User_0 ; User Interrupt 0 64 DC.L _INT_User_1 ; User Interrupt 1 65 DC.L _INT_User_2 ; User Interrupt 2 66 DC.L _INT_User_3 ; User Interrupt 3 67 DC.L _INT_User_4 ; User Interrupt 4 68 DC.L _INT_User_5 ; User Interrupt 5 69 DC.L _INT_User_6 ; User Interrupt 6 70⌨️ 快捷键说明
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