mcf5307.h

mcf5307开发板diab4.2开发环境下led的测试程序

/*									*/
/*  Timer Registers							*/
/*									*/
/************************************************************************/

typedef volatile struct
{
	NATURAL32	reserved0[0x50];
	NATURAL16	TMR1;		/* Timer 1 Mode Register	*/
	NATURAL16	reserved1;
	NATURAL16	TRR1;		/* Timer 1 Reference Register	*/
	NATURAL16	reserved2;
	NATURAL16	TCR1;		/* Timer 1 Capture Register	*/
	NATURAL16	reserved3;
	NATURAL16	TCN1;		/* Timer 1 Counter		*/
	NATURAL16	reserved4;
	NATURAL8	reserved5;
	NATURAL8	TER1;		/* Timer 1 Event Register	*/
	NATURAL16	reserved6;
	NATURAL32	reserved7[0xb];
	NATURAL16	TMR2;		/* Timer 2 Mode Register	*/
	NATURAL16	reserved8;
	NATURAL16	TRR2;		/* Timer 2 Reference Register	*/
	NATURAL16	reserved9;
	NATURAL16	TCR2;		/* Timer 2 Capture Register	*/
	NATURAL16	reserved10;
	NATURAL16	TCN2;		/* Timer 2 Counter		*/
	NATURAL16	reserved11;
	NATURAL8	reserved12;
	NATURAL8	TER2;		/* Timer 2 Event Register	*/
} MCF5307_TIMER;

#define MCF5307_TIMER_TMR_PS(a)		(((a)&0x00FF)<<8) /* Prescaler Value		*/
#define MCF5307_TIMER_TMR_CE_ANY	(0x00C0) /* Capture on Any Edge			*/
#define MCF5307_TIMER_TMR_CE_FALL	(0x0080) /* Capture on Falling Edge		*/
#define MCF5307_TIMER_TMR_CE_RISE	(0x0040) /* Capture on Rising Edge		*/
#define MCF5307_TIMER_TMR_CE_NONE	(0x0000) /* Disable Capture Event		*/
#define MCF5307_TIMER_TMR_OM		(0x0020) /* Output Mode				*/
#define MCF5307_TIMER_TMR_ORI		(0x0010) /* Output Reference Interrupt Enable	*/
#define MCF5307_TIMER_TMR_FRR		(0x0008) /* Restart After Reference Value	*/
#define MCF5307_TIMER_TMR_CLK_TIN	(0x0006) /* TIN is Input Clock Source		*/
#define MCF5307_TIMER_TMR_CLK_DIV16	(0x0004) /* Sys Clk / 16 is Input Clock Source	*/
#define MCF5307_TIMER_TMR_CLK_MSCLK	(0x0002) /* Sys Clk is Input Clock Source	*/
#define MCF5307_TIMER_TMR_CLK_STOP	(0x0000) /* Stop Count				*/
#define MCF5307_TIMER_TMR_RST		(0x0001) /* Enable Timer			*/
						 /* H to L will Reset Registers		*/

#define MCF5307_TIMER_TER_REF		(0x02)	/* Output Reference Event		*/
#define MCF5307_TIMER_TER_CAP		(0x01)	/* Capture Event			*/


/****************************************************************************************/
/*											*/
/*  UART Registers									*/
/*	Several UART registers contain overlapped information for receiving (reads) and	*/
/*	transmitting (writes).  To see the programming process, please refer to the	*/
/*	User's manual.									*/
/*											*/
/****************************************************************************************/

typedef volatile struct
{
	NATURAL32	reserved0[0x70];
	NATURAL8	UMR11_UMR21;	/* UART 1 (Receive / Transmit) Mode Register	*/
	NATURAL8	reserved1;
	NATURAL16	reserved2;
	NATURAL8	USR1_UCSR1;	/* UART 1 (Status / Clock-Select) Register	*/
	NATURAL8	reserved3;
	NATURAL16	reserved4;
	NATURAL8	UCR1;		/* UART 1 ( -- / Command) Register		*/
	NATURAL8	reserved5;
	NATURAL16	reserved6;
	NATURAL8	URB1_UTB1;	/* UART 1 (Receive / Transmit) Buffer		*/
	NATURAL8	reserved7;
	NATURAL16	reserved8;
	NATURAL8	UIPCR1_UACR1;	/* UART 1 (Input Port Change / Aux Control) Reg	*/
	NATURAL8	reserved9;
	NATURAL16	reserved10;
	NATURAL8	UISR1_UIMR1;	/* UART 1 (Interrupt Status / Interrupt Mask)	*/
	NATURAL8	reserved11;
	NATURAL16	reserved12;
	NATURAL8	UBG11;		/* UART 1 Baud Rate Generator Prescale MSB	*/
	NATURAL8	reserved13;
	NATURAL16	reserved14;
	NATURAL8	UBG21;		/* UART 1 Baud Rate Generator Prescale LSB	*/
					/* The minimum value for UBG concatenated is 2	*/
	NATURAL8	reserved15;
	NATURAL16	reserved16;
	NATURAL32	reserved17[4];
	NATURAL8	UIVR1;		/* UART 1 (Interrupt Vector / ") Register	*/
	NATURAL8	reserved18;
	NATURAL16	reserved19;
	NATURAL8	UIP1;		/* UART 1 (Input Port / --) Register		*/
	NATURAL8	reserved20;
	NATURAL16	reserved21;
	NATURAL8	UOP11;		/* UART 1 (-- / Output Port Bit Set Command)	*/
	NATURAL8	reserved22;
	NATURAL16	reserved23;
	NATURAL8	UOP01;		/* UART 1 (-- / Output Port Bit Reset Command)	*/
} MCF5307_UART1;

typedef volatile struct
{
	NATURAL32	reserved0[0x80];
	NATURAL8	UMR12_UMR22;	/* UART 2 (Receive / Transmit) Mode Register	*/
	NATURAL8	reserved1;
	NATURAL16	reserved2;
	NATURAL8	USR2_UCSR2;	/* UART 2 (Status / Clock-Select) Register	*/
	NATURAL8	reserved3;
	NATURAL16	reserved4;
	NATURAL8	UCR2;		/* UART 2 ( -- / Command) Register		*/
	NATURAL8	reserved5;
	NATURAL16	reserved6;
	NATURAL8	URB2_UTB2;	/* UART 2 (Receive / Transmit) Buffer		*/
	NATURAL8	reserved7;
	NATURAL16	reserved8;
	NATURAL8	UIPCR2_UACR2;	/* UART 2 (Input Port Change / Aux Control) Reg	*/
	NATURAL8	reserved9;
	NATURAL16	reserved10;
	NATURAL8	UISR2_UIMR2;	/* UART 2 (Interrupt Status / Interrupt Mask)	*/
	NATURAL8	reserved11;
	NATURAL16	reserved12;
	NATURAL8	UBG12;		/* UART 2 Baud Rate Generator Prescale MSB	*/
	NATURAL8	reserved13;
	NATURAL16	reserved14;
	NATURAL8	UBG22;		/* UART 2 Baud Rate Generator Prescale LSB	*/
					/* The minimum value for UBG concatenated is 2	*/
	NATURAL8	reserved15;
	NATURAL16	reserved16;
	NATURAL32	reserved17[4];
	NATURAL8	UIVR2;		/* UART 2 (Interrupt Vector / ") Register	*/
	NATURAL8	reserved18;
	NATURAL16	reserved19;
	NATURAL8	UIP2;		/* UART 2 (Input Port / --) Register		*/
	NATURAL8	reserved20;
	NATURAL16	reserved21;
	NATURAL8	UOP12;		/* UART 2 (-- / Output Port Bit Set Command)	*/
	NATURAL8	reserved22;
	NATURAL16	reserved23;
	NATURAL8	UOP02;		/* UART 2 (-- / Output Port Bit Reset Command)	*/
} MCF5307_UART2;

 /***********************************************************************/
 /*									*/
 /*  In the first register, UMR1 is for reads and UMR2 is for writes.	*/
 /*									*/
 /***********************************************************************/

#define MCF5307_UART_UMR1_RXRTS			(0x80)	/* Receive Request-to-Send	*/
#define MCF5307_UART_UMR1_RXIRQ			(0x40)	/* Receive Interrupt Select	*/
#define MCF5307_UART_UMR1_ERR			(0x20)	/* Error Mode			*/
#define MCF5307_UART_UMR1_PM_MULTI_ADDR		(0x1C)	/* Parity: Multidrop Adr Char	*/
#define MCF5307_UART_UMR1_PM_MULTI_DATA		(0x18)	/* Parity: Multidrop Data Char	*/
#define MCF5307_UART_UMR1_PM_NONE		(0x10)	/* Parity: None			*/
#define MCF5307_UART_UMR1_PM_FORCE_HI		(0x0C)	/* Parity: Force High		*/
#define MCF5307_UART_UMR1_PM_FORCE_LO		(0x08)	/* Parity: Force Low		*/
#define MCF5307_UART_UMR1_PM_ODD		(0x04)	/* Parity: Odd Parity		*/
#define MCF5307_UART_UMR1_PM_EVEN		(0x00)	/* Parity: Even Parity		*/
#define MCF5307_UART_UMR1_BC_5			(0x00)	/* 5 Bits Per Character		*/
#define MCF5307_UART_UMR1_BC_6			(0x01)	/* 6 Bits Per Character		*/
#define MCF5307_UART_UMR1_BC_7			(0x02)	/* 7 Bits Per Character		*/
#define MCF5307_UART_UMR1_BC_8			(0x03)	/* 8 Bits Per Character		*/

#define MCF5307_UART_UMR2_CM_NORMAL		(0x00)	/* Normal Channel Mode		*/
#define MCF5307_UART_UMR2_CM_ECHO		(0x40)	/* Automatic Echo Channel Mode	*/
#define MCF5307_UART_UMR2_CM_LOCAL_LOOP		(0x80)	/* Local Loopback Channel Mode	*/
#define MCF5307_UART_UMR2_CM_REMOTE_LOOP	(0xC0)	/* Remote Loopback Channel Mode	*/
#define MCF5307_UART_UMR2_TXRTS			(0x20)	/* Transmitter Ready-to-Send	*/
#define MCF5307_UART_UMR2_TXCTS			(0x10)	/* Transmitter Clear-to-Send	*/
#define MCF5307_UART_UMR2_STOP_BITS_2		(0x0F)	/* 2 Stop Bits			*/
#define MCF5307_UART_UMR2_STOP_BITS(a)		((a)&0x0f)	/* Stop Bit Length	*/

 /***********************************************************************/
 /*									*/
 /*  In this next register, USR is for reads and UCSR is for writes.	*/
 /*									*/
 /***********************************************************************/

#define MCF5307_UART_USR_RB			(0x80)	/* Received Break		*/
#define MCF5307_UART_USR_FE			(0x40)	/* Framing Error		*/
#define MCF5307_UART_USR_PE			(0x20)	/* Parity Error			*/
#define MCF5307_UART_USR_OE			(0x10)	/* Overrun Error		*/
#define MCF5307_UART_USR_TXEMP			(0x08)	/* Transmitter Empty		*/
#define MCF5307_UART_USR_TXRDY			(0x04)	/* Transmitter Ready		*/
#define MCF5307_UART_USR_FFULL			(0x02)	/* FIFO Full			*/
#define MCF5307_UART_USR_RXRDY			(0x01)	/* Receiver Ready		*/

#define MCF5307_UART_UCSR_9600_BPS		(0xBB)	/* 9600 Baud w/ 3.6864 MHz clk	*/
#define MCF5307_UART_UCSR_RCS(a)		(((a)&0x0f)<<4) /* Receiver Clk Select	*/
#define MCF5307_UART_UCSR_TCS(a)		((a)&0x0f) /* Transmitter Clock Select	*/

 /***********************************************************************/
 /*									*/
 /*  In this next register, there is only UCR is for writes.		*/
 /*									*/
 /***********************************************************************/

#define MCF5307_UART_UCR_NONE			(0x00)	/* No Command			*/
#define MCF5307_UART_UCR_STOP_BREAK		(0x70)	/* Stop Break			*/
#define MCF5307_UART_UCR_START_BREAK		(0x60)	/* Start Break			*/
#define MCF5307_UART_UCR_RESET_BKCHGINT		(0x50)	/* Reset Break-Change Interrupt	*/
#define MCF5307_UART_UCR_RESET_ERROR		(0x40)	/* Reset Error Status		*/
#define MCF5307_UART_UCR_RESET_TX		(0x30)	/* Reset Transmitter		*/
#define MCF5307_UART_UCR_RESET_RX		(0x20)	/* Reset Receiver		*/
#define MCF5307_UART_UCR_RESET_MR		(0x10)	/* Reset Mode Register Pointer	*/
#define MCF5307_UART_UCR_TX_DISABLED		(0x08)	/* Transmitter Disabled		*/
#define MCF5307_UART_UCR_TX_ENABLED		(0x04)	/* Transmitter Enabled		*/
#define MCF5307_UART_UCR_RX_DISABLED		(0x02)	/* Receiver Disabled		*/
#define MCF5307_UART_UCR_RX_ENABLED		(0x01)	/* Receiver Enabled		*/

 /***********************************************************************/
 /*									*/
 /*  In this next register, UIPCR is for reads and UACR is for writes.	*/
 /*									*/
 /***********************************************************************/

#define MCF5307_UART_UIPCR_COS			(0x10)	/* Change-of-State at IPx input	*/
#define MCF5307_UART_UIPCR_CTS			(0x01)	/* Current State of CTS pin	*/

#define MCF5307_UART_UACR_BRG			(0x80)	/* Set 2 of Baud Rate Generator	*/
#define MCF5307_UART_UACR_CTMS_TIMER		(0x60)	/* Timer Mode and Source Select	*/
							/* Must set this mode and src	*/
#define MCF5307_UART_UACR_IEC			(0x01)	/* Input Enable Control		*/

 /***********************************************************************/
 /*									*/
 /*  In this next register, UISR is for reads and UIMR is for writes.	*/
 /*									*/
 /***********************************************************************/

#define MCF5307_UART_UISR_COS			(0x80)	/* Change-of-State at CTS input	*/
#define MCF5307_UART_UISR_DB			(0x04)	/* Receiver Has Detected Break	*/
#define MCF5307_UART_UISR_RXRDY			(0x02)	/* Receiver Ready or FIFO Full	*/
#define MCF5307_UART_UISR_TXRDY			(0x01)	/* Transmitter Ready		*/

#define MCF5307_UART_UIMR_COS			(0x80)	/* Enable Change-of-State Intpt	*/
#define MCF5307_UART_UIMR_DB			(0x04)	/* Enable Delta Break Interrupt	*/
#define MCF5307_UART_UIMR_FFULL			(0x02)	/* Enable FIFO Full Interrupt	*/
#define MCF5307_UART_UIMR_TXRDY			(0x01)	/* Enable Transmitter Rdy Intpt	*/

 /*******************************************************************************/
 /*										*/
 /*  The last few registers can only be accessed as a read or write register.	*/
 /*										*/
 /*******************************************************************************/

#define MCF5307_UART_UIP_CTS			(0x01) /* Current State of CTS Input	*/

#define MCF5307_UART_UOP_RTS			(0x01) /* Sets All Bits on OP Bit Set	*/
#define MCF5307_UART_UOP0_RTS			(0x01) /* Clears All Bits on OP Bit Rst	*/


/************************************************************************/
/*									*/
/*  Parallel Port Registers						*/
/*									*/
/************************************************************************/

typedef volatile struct
{
	NATURAL32	reserved0[0x91];
	NATURAL16	PADDR;		/* Port A Data Direction Register	*/
	NATURAL16	reserved1;
	NATURAL16	PADAT;		/* Port A Data Register			*/
	NATURAL16	reserved2;
} MCF5307_PPORT;

#define MCF5307_PPORT_PADDR_15	(0x8000)	/* Bit 15 General I/O Output	*/
#define MCF5307_PPORT_PADDR_14	(0x4000)	/* Bit 14 General I/O Output	*/
#define MCF5307_PPORT_PADDR_13	(0x2000)	/* Bit 13 General I/O Output	*/
#define MCF5307_PPORT_PADDR_12	(0x1000)	/* Bit 12 General I/O Output	*/