hdb3.map.rpt

基于VHDL语言的HDB3码编译码器的设计 HDB3 码的全称是三阶高密度双极性码

+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 2:1                ; 2 bits    ; 2 LEs         ; 2 LEs                ; 0 LEs                  ; Yes        ; |hdb3|REG_POS[3]           ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |hdb3|CNT0[0]              ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |hdb3|POS_OUT_TEMP         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 0     ;
; Number of synthesis-generated cells                    ; 24    ;
; Number of WYSIWYG LUTs                                 ; 0     ;
; Number of synthesis-generated LUTs                     ; 12    ;
; Number of WYSIWYG registers                            ; 0     ;
; Number of synthesis-generated registers                ; 19    ;
; Number of cells with combinational logic only          ; 5     ;
; Number of cells with registers only                    ; 12    ;
; Number of cells with combinational logic and registers ; 7     ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 19    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 4     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
hdb3


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |hdb3                      ; 24 (24)     ; 19           ; 0           ; 4    ; 0            ; 5 (5)        ; 12 (12)           ; 7 (7)            ; 0 (0)           ; |hdb3               ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/altera/hdb3/hdb3.map.eqn.


+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                            ;
+----------------------------------+-----------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------+
; HDB3.vhd                         ; yes             ; F:/altera/hdb3/HDB3.vhd      ;
+----------------------------------+-----------------+------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Logic cells                     ; 24        ;
; Total combinational functions   ; 12        ;
; Total 4-input functions         ; 4         ;
; Total 3-input functions         ; 4         ;
; Total 2-input functions         ; 4         ;
; Total 1-input functions         ; 0         ;
; Total 0-input functions         ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 19        ;
; I/O pins                        ; 4         ;
; Maximum fan-out node            ; clk       ;
; Maximum fan-out                 ; 19        ;
; Total fan-out                   ; 73        ;
; Average fan-out                 ; 2.61      ;
+---------------------------------+-----------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Fri Jul 15 01:16:42 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off hdb3 -c hdb3
Info: Found 2 design units, including 1 entities, in source file HDB3.vhd
    Info: Found design unit 1: hdb3-A
    Info: Found entity 1: hdb3
Info: Duplicate registers merged to single register
    Info: Duplicate register "JJ22" merged to single register "CNT1", power-up level changed
Info: Implemented 28 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 2 output pins
    Info: Implemented 24 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Fri Jul 15 01:16:52 2005
    Info: Elapsed time: 00:00:11