hdb3.vhd

基于VHDL语言的HDB3码编译码器的设计 HDB3 码的全称是三阶高密度双极性码

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity hdb3 is
port(clk: in std_logic;
     data_in: in std_logic;
     pos_out,neg_out: out  std_logic);
end ENTITY hdb3;

ARCHITECTURE A of hdb3 is
   SIGNAL CNT1: STD_LOGIC;
   SIGNAL CNT0: STD_LOGIC_VECTOR(1 DOWNTO 0);
   SIGNAL JJ22,REGVV,FLAG: STD_LOGIC;
   SIGNAL POS_OUT_TEMP,NEG_OUT_TEMP: STD_LOGIC;
   SIGNAL REG_POS: STD_LOGIC_VECTOR(3 DOWNTO 0);
   SIGNAL REG_NEG: STD_LOGIC_VECTOR(3 DOWNTO 0);
   SIGNAL CTL,B: STD_LOGIC;

BEGIN

   U1: PROCESS(CLK)
     BEGIN 
       IF CLK'EVENT AND CLK='1' THEN 
          	  IF DATA_IN='0' THEN                  --输入信号为0时
                 CNT0<=CNT0+1;
              	   IF  CNT0="11" THEN              --四个连0产生
                	   CNT0<="00";
                       REGVV<=NOT CNT1;
                 		IF JJ22=NOT REGVV  THEN    --两个V之间有奇数个非0
                    		FLAG<='0';
                    		CTL<='0';
                     		IF CNT1='1'    THEN    -- +V
                        		POS_OUT_TEMP<='1';                  
                        		NEG_OUT_TEMP<='0';
                     		ELSE                   -- -V
                        		POS_OUT_TEMP<='0';                  
                        		NEG_OUT_TEMP<='1';
         			 		END IF;  
                  		ELSE                       --两个V之间有偶数个非0
             	    			FLAG<='1';
                    			CTL<='1';
                    			B<=CNT1 NOR FLAG;
                    		IF CNT1='0'    THEN    -- +V
                        		POS_OUT_TEMP<='1';                  
                       			NEG_OUT_TEMP<='0';
                     		ELSE                   -- -V
                        		POS_OUT_TEMP<='0';                  
                        		NEG_OUT_TEMP<='1';
         			 		END IF; 
                  		END IF;   
                    ELSE
                        CTL<='0';
                        POS_OUT_TEMP<='0';                  
                        NEG_OUT_TEMP<='0';
                    END IF;   
                           
          	   ELSE                             --输入信号为1时
                        CTL<='0';
						CNT0<="00";
						CNT1<=NOT CNT1;
						JJ22<=CNT1;
						--FLAG='0'时，对1的处理和AMI码相同
						--FLAG='1'时,说明两个V之间有偶数个非0，对1的处理和AMI码相反
					IF  FLAG='0' THEN 
					        IF CNT1='0'     THEN
                        		POS_OUT_TEMP<='1';                  
                       			NEG_OUT_TEMP<='0';
                     		ELSE
                        		POS_OUT_TEMP<='0';                  
                        		NEG_OUT_TEMP<='1';
         			 		END IF; 
                     ELSE 
							IF CNT1='0'     THEN
                        		POS_OUT_TEMP<='0';                  
                       			NEG_OUT_TEMP<='1';
                     		ELSE
                        		POS_OUT_TEMP<='1';                  
                        		NEG_OUT_TEMP<='0';
         			 		END IF; 
					END IF; 
              END IF; 
       END IF; 
  END PROCESS;
  --移位寄存器进程
  --CTL='0',不需要添加B信号，不改变POS_OUT_TEMP,NEG_OUT_TEMP中的值
  --CTL='1',需要添加B信号，根据B的正负，改变POS_OUT_TEMP,NEG_OUT_TEMP,使输出加上+B,-B
  U2:  PROCESS(CLK)
  BEGIN 
     IF CLK'EVENT AND CLK='1' THEN
     	REG_POS(0)<=POS_OUT_TEMP;
     	REG_NEG(0)<=NEG_OUT_TEMP;
    	FOR I IN 1 TO 3  LOOP
         	REG_POS(I)<=REG_POS(I-1);
         	REG_NEG(I)<=REG_NEG(I-1);
     	END LOOP;
     	IF CTL='1'  THEN 
        	IF B='1' THEN
           		REG_POS(3)<='1';
           		REG_NEG(3)<='0';
        	ELSE 
           		REG_POS(3)<='0';
           		REG_NEG(3)<='1';
        	END IF; 
     	END IF;
     POS_OUT<=REG_POS(3);
     NEG_OUT<=REG_NEG(3);
 END IF;
END PROCESS;  			    	
 END A;