hdb3.tan.rpt

基于VHDL语言的HDB3码编译码器的设计 HDB3 码的全称是三阶高密度双极性码

; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT1         ; FLAG         ; clk        ; clk      ; None                        ; None                      ; 1.040 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT1         ; CNT1         ; clk        ; clk      ; None                        ; None                      ; 1.038 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CTL          ; REG_NEG[3]   ; clk        ; clk      ; None                        ; None                      ; 1.025 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; REG_POS[2]   ; REG_POS[3]   ; clk        ; clk      ; None                        ; None                      ; 1.016 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; NEG_OUT_TEMP ; REG_NEG[0]   ; clk        ; clk      ; None                        ; None                      ; 0.870 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; REG_NEG[0]   ; REG_NEG[1]   ; clk        ; clk      ; None                        ; None                      ; 0.825 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; REG_POS[0]   ; REG_POS[1]   ; clk        ; clk      ; None                        ; None                      ; 0.825 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; REGVV        ; FLAG         ; clk        ; clk      ; None                        ; None                      ; 0.825 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; REG_POS[1]   ; REG_POS[2]   ; clk        ; clk      ; None                        ; None                      ; 0.658 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; REG_POS[3]   ; pos_out~reg0 ; clk        ; clk      ; None                        ; None                      ; 0.657 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; REG_NEG[1]   ; REG_NEG[2]   ; clk        ; clk      ; None                        ; None                      ; 0.652 ns                ;
+-------+------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------+
; tsu                                                                   ;
+-------+--------------+------------+---------+--------------+----------+
; Slack ; Required tsu ; Actual tsu ; From    ; To           ; To Clock ;
+-------+--------------+------------+---------+--------------+----------+
; N/A   ; None         ; 5.902 ns   ; data_in ; B            ; clk      ;
; N/A   ; None         ; 5.552 ns   ; data_in ; REGVV        ; clk      ;
; N/A   ; None         ; 5.552 ns   ; data_in ; FLAG         ; clk      ;
; N/A   ; None         ; 4.897 ns   ; data_in ; NEG_OUT_TEMP ; clk      ;
; N/A   ; None         ; 4.895 ns   ; data_in ; POS_OUT_TEMP ; clk      ;
; N/A   ; None         ; 4.208 ns   ; data_in ; CNT1         ; clk      ;
; N/A   ; None         ; 4.157 ns   ; data_in ; CNT0[1]      ; clk      ;
; N/A   ; None         ; 4.153 ns   ; data_in ; CNT0[0]      ; clk      ;
; N/A   ; None         ; 4.146 ns   ; data_in ; CTL          ; clk      ;
+-------+--------------+------------+---------+--------------+----------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 6.661 ns   ; neg_out~reg0 ; neg_out ; clk        ;
; N/A   ; None         ; 6.481 ns   ; pos_out~reg0 ; pos_out ; clk        ;
+-------+--------------+------------+--------------+---------+------------+


+-----------------------------------------------------------------------------+
; th                                                                          ;
+---------------+-------------+-----------+---------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To           ; To Clock ;
+---------------+-------------+-----------+---------+--------------+----------+
; N/A           ; None        ; -4.087 ns ; data_in ; NEG_OUT_TEMP ; clk      ;
; N/A           ; None        ; -4.094 ns ; data_in ; CTL          ; clk      ;
; N/A           ; None        ; -4.096 ns ; data_in ; POS_OUT_TEMP ; clk      ;
; N/A           ; None        ; -4.101 ns ; data_in ; CNT0[0]      ; clk      ;
; N/A           ; None        ; -4.105 ns ; data_in ; CNT0[1]      ; clk      ;
; N/A           ; None        ; -4.156 ns ; data_in ; CNT1         ; clk      ;
; N/A           ; None        ; -5.500 ns ; data_in ; REGVV        ; clk      ;
; N/A           ; None        ; -5.500 ns ; data_in ; FLAG         ; clk      ;
; N/A           ; None        ; -5.850 ns ; data_in ; B            ; clk      ;
+---------------+-------------+-----------+---------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Fri Jul 15 01:17:20 2005
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off hdb3 -c hdb3 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 241.37 MHz between source register "CNT0[0]" and destination register "B" (period= 4.143 ns)
    Info: + Longest register to register delay is 3.882 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y9_N4; Fanout = 4; REG Node = 'CNT0[0]'
        Info: 2: + IC(0.576 ns) + CELL(0.292 ns) = 0.868 ns; Loc. = LC_X2_Y9_N1; Fanout = 5; COMB Node = 'POS_OUT_TEMP~104'
        Info: 3: + IC(0.473 ns) + CELL(0.590 ns) = 1.931 ns; Loc. = LC_X2_Y9_N7; Fanout = 1; COMB Node = 'B~1'
        Info: 4: + IC(1.084 ns) + CELL(0.867 ns) = 3.882 ns; Loc. = LC_X2_Y9_N6; Fanout = 2; REG Node = 'B'
        Info: Total cell delay = 1.749 ns ( 45.05 % )
        Info: Total interconnect delay = 2.133 ns ( 54.95 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.767 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 19; CLK Node = 'clk'
            Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X2_Y9_N6; Fanout = 2; REG Node = 'B'
            Info: Total cell delay = 2.180 ns ( 78.79 % )
            Info: Total interconnect delay = 0.587 ns ( 21.21 % )
        Info: - Longest clock path from clock "clk" to source register is 2.767 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 19; CLK Node = 'clk'
            Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X2_Y9_N4; Fanout = 4; REG Node = 'CNT0[0]'
            Info: Total cell delay = 2.180 ns ( 78.79 % )
            Info: Total interconnect delay = 0.587 ns ( 21.21 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "B" (data pin = "data_in", clock pin = "clk") is 5.902 ns
    Info: + Longest pin to register delay is 8.632 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 9; PIN Node = 'data_in'
        Info: 2: + IC(5.098 ns) + CELL(0.114 ns) = 6.681 ns; Loc. = LC_X2_Y9_N7; Fanout = 1; COMB Node = 'B~1'
        Info: 3: + IC(1.084 ns) + CELL(0.867 ns) = 8.632 ns; Loc. = LC_X2_Y9_N6; Fanout = 2; REG Node = 'B'
        Info: Total cell delay = 2.450 ns ( 28.38 % )
        Info: Total interconnect delay = 6.182 ns ( 71.62 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.767 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 19; CLK Node = 'clk'
        Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X2_Y9_N6; Fanout = 2; REG Node = 'B'
        Info: Total cell delay = 2.180 ns ( 78.79 % )
        Info: Total interconnect delay = 0.587 ns ( 21.21 % )
Info: tco from clock "clk" to destination pin "neg_out" through register "neg_out~reg0" is 6.661 ns
    Info: + Longest clock path from clock "clk" to source register is 2.730 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 19; CLK Node = 'clk'
        Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X1_Y5_N2; Fanout = 1; REG Node = 'neg_out~reg0'
        Info: Total cell delay = 2.180 ns ( 79.85 % )
        Info: Total interconnect delay = 0.550 ns ( 20.15 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.707 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y5_N2; Fanout = 1; REG Node = 'neg_out~reg0'
        Info: 2: + IC(1.583 ns) + CELL(2.124 ns) = 3.707 ns; Loc. = PIN_27; Fanout = 0; PIN Node = 'neg_out'
        Info: Total cell delay = 2.124 ns ( 57.30 % )
        Info: Total interconnect delay = 1.583 ns ( 42.70 % )
Info: th for register "NEG_OUT_TEMP" (data pin = "data_in", clock pin = "clk") is -4.087 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.767 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 19; CLK Node = 'clk'
        Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X2_Y9_N5; Fanout = 1; REG Node = 'NEG_OUT_TEMP'
        Info: Total cell delay = 2.180 ns ( 78.79 % )
        Info: Total interconnect delay = 0.587 ns ( 21.21 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 6.869 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 9; PIN Node = 'data_in'
        Info: 2: + IC(5.091 ns) + CELL(0.309 ns) = 6.869 ns; Loc. = LC_X2_Y9_N5; Fanout = 1; REG Node = 'NEG_OUT_TEMP'
        Info: Total cell delay = 1.778 ns ( 25.88 % )
        Info: Total interconnect delay = 5.091 ns ( 74.12 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Jul 15 01:17:21 2005
    Info: Elapsed time: 00:00:01