📄 hdb3.tan.rpt
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Timing Analyzer report for hdb3
Fri Jul 15 01:17:21 2005
Version 4.2 Build 157 12/07/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+--------------+--------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+--------------+--------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 5.902 ns ; data_in ; B ; ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 6.661 ns ; neg_out~reg0 ; neg_out ; clk ; ; 0 ;
; Worst-case th ; N/A ; None ; -4.087 ns ; data_in ; NEG_OUT_TEMP ; ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; 241.37 MHz ( period = 4.143 ns ) ; CNT0[0] ; B ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+--------------+--------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C3T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minumum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Clock Analysis Only ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off clear and preset signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Do Min/Max analysis using Rise/Fall delays ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Use Clock Latency for PLL offset ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 241.37 MHz ( period = 4.143 ns ) ; CNT0[0] ; B ; clk ; clk ; None ; None ; 3.882 ns ;
; N/A ; 254.52 MHz ( period = 3.929 ns ) ; CNT0[1] ; B ; clk ; clk ; None ; None ; 3.668 ns ;
; N/A ; 272.48 MHz ( period = 3.670 ns ) ; REGVV ; B ; clk ; clk ; None ; None ; 3.409 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT1 ; B ; clk ; clk ; None ; None ; 3.216 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT1 ; NEG_OUT_TEMP ; clk ; clk ; None ; None ; 2.950 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT1 ; POS_OUT_TEMP ; clk ; clk ; None ; None ; 2.948 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT0[0] ; NEG_OUT_TEMP ; clk ; clk ; None ; None ; 2.859 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT0[0] ; POS_OUT_TEMP ; clk ; clk ; None ; None ; 2.857 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; REGVV ; NEG_OUT_TEMP ; clk ; clk ; None ; None ; 2.726 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; REGVV ; POS_OUT_TEMP ; clk ; clk ; None ; None ; 2.724 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT0[1] ; NEG_OUT_TEMP ; clk ; clk ; None ; None ; 2.645 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT0[1] ; POS_OUT_TEMP ; clk ; clk ; None ; None ; 2.643 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT0[1] ; FLAG ; clk ; clk ; None ; None ; 2.561 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT0[1] ; REGVV ; clk ; clk ; None ; None ; 2.561 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT0[0] ; FLAG ; clk ; clk ; None ; None ; 2.459 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT0[0] ; REGVV ; clk ; clk ; None ; None ; 2.459 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; FLAG ; NEG_OUT_TEMP ; clk ; clk ; None ; None ; 2.404 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; FLAG ; POS_OUT_TEMP ; clk ; clk ; None ; None ; 2.402 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; REG_NEG[3] ; neg_out~reg0 ; clk ; clk ; None ; None ; 2.330 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT0[0] ; CTL ; clk ; clk ; None ; None ; 2.079 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT0[1] ; CTL ; clk ; clk ; None ; None ; 1.865 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CTL ; REG_POS[3] ; clk ; clk ; None ; None ; 1.794 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; FLAG ; B ; clk ; clk ; None ; None ; 1.655 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; REGVV ; CTL ; clk ; clk ; None ; None ; 1.644 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; POS_OUT_TEMP ; REG_POS[0] ; clk ; clk ; None ; None ; 1.521 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; B ; REG_POS[3] ; clk ; clk ; None ; None ; 1.521 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT1 ; CTL ; clk ; clk ; None ; None ; 1.430 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; B ; REG_NEG[3] ; clk ; clk ; None ; None ; 1.286 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT0[1] ; CNT0[1] ; clk ; clk ; None ; None ; 1.130 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; REG_NEG[2] ; REG_NEG[3] ; clk ; clk ; None ; None ; 1.106 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT0[0] ; CNT0[1] ; clk ; clk ; None ; None ; 1.055 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT0[0] ; CNT0[0] ; clk ; clk ; None ; None ; 1.052 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CNT1 ; REGVV ; clk ; clk ; None ; None ; 1.043 ns ;
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