hdb3.map.eqn

基于VHDL语言的HDB3码编译码器的设计 HDB3 码的全称是三阶高密度双极性码

--A1L91Q is pos_out~reg0
--operation mode is normal

A1L91Q_lut_out = REG_POS[3];
A1L91Q = DFFEAS(A1L91Q_lut_out, clk, VCC, , , , , , );


--A1L31Q is neg_out~reg0
--operation mode is normal

A1L31Q_lut_out = REG_NEG[3];
A1L31Q = DFFEAS(A1L31Q_lut_out, clk, VCC, , , , , , );


--REG_POS[3] is REG_POS[3]
--operation mode is normal

REG_POS[3]_lut_out = CTL & B # !CTL & REG_POS[2];
REG_POS[3] = DFFEAS(REG_POS[3]_lut_out, clk, VCC, , , , , , );


--REG_NEG[3] is REG_NEG[3]
--operation mode is normal

REG_NEG[3]_lut_out = CTL & !B # !CTL & REG_NEG[2];
REG_NEG[3] = DFFEAS(REG_NEG[3]_lut_out, clk, VCC, , , , , , );


--B is B
--operation mode is normal

B_lut_out = !FLAG & !CNT1;
B = DFFEAS(B_lut_out, clk, VCC, , A1L2, , , , );


--REG_POS[2] is REG_POS[2]
--operation mode is normal

REG_POS[2]_lut_out = REG_POS[1];
REG_POS[2] = DFFEAS(REG_POS[2]_lut_out, clk, VCC, , , , , , );


--CTL is CTL
--operation mode is normal

CTL_lut_out = A1L2;
CTL = DFFEAS(CTL_lut_out, clk, VCC, , , , , , );


--REG_NEG[2] is REG_NEG[2]
--operation mode is normal

REG_NEG[2]_lut_out = REG_NEG[1];
REG_NEG[2] = DFFEAS(REG_NEG[2]_lut_out, clk, VCC, , , , , , );


--FLAG is FLAG
--operation mode is normal

FLAG_lut_out = A1L13;
FLAG = DFFEAS(FLAG_lut_out, clk, VCC, , A1L71, , , , );


--CNT1 is CNT1
--operation mode is normal

CNT1_lut_out = !CNT1;
CNT1 = DFFEAS(CNT1_lut_out, clk, VCC, , data_in, , , , );


--CNT0[0] is CNT0[0]
--operation mode is normal

CNT0[0]_lut_out = !data_in & !CNT0[0];
CNT0[0] = DFFEAS(CNT0[0]_lut_out, clk, VCC, , , , , , );


--CNT0[1] is CNT0[1]
--operation mode is normal

CNT0[1]_lut_out = !data_in & CNT0[0] $ CNT0[1];
CNT0[1] = DFFEAS(CNT0[1]_lut_out, clk, VCC, , , , , , );


--A1L61 is POS_OUT_TEMP~104
--operation mode is normal

A1L61 = CNT0[0] & CNT0[1];


--REGVV is REGVV
--operation mode is normal

REGVV_lut_out = !CNT1;
REGVV = DFFEAS(REGVV_lut_out, clk, VCC, , A1L71, , , , );


--A1L2 is B~1
--operation mode is normal

A1L2 = A1L61 & !data_in & CNT1 $ REGVV;


--REG_POS[1] is REG_POS[1]
--operation mode is normal

REG_POS[1]_lut_out = REG_POS[0];
REG_POS[1] = DFFEAS(REG_POS[1]_lut_out, clk, VCC, , , , , , );


--REG_NEG[1] is REG_NEG[1]
--operation mode is normal

REG_NEG[1]_lut_out = REG_NEG[0];
REG_NEG[1] = DFFEAS(REG_NEG[1]_lut_out, clk, VCC, , , , , , );


--A1L13 is U1~0
--operation mode is normal

A1L13 = CNT1 $ REGVV;


--A1L71 is POS_OUT_TEMP~105
--operation mode is normal

A1L71 = CNT0[0] & CNT0[1] & !data_in;


--REG_POS[0] is REG_POS[0]
--operation mode is normal

REG_POS[0]_lut_out = POS_OUT_TEMP;
REG_POS[0] = DFFEAS(REG_POS[0]_lut_out, clk, VCC, , , , , , );


--REG_NEG[0] is REG_NEG[0]
--operation mode is normal

REG_NEG[0]_lut_out = NEG_OUT_TEMP;
REG_NEG[0] = DFFEAS(REG_NEG[0]_lut_out, clk, VCC, , , , , , );


--POS_OUT_TEMP is POS_OUT_TEMP
--operation mode is normal

POS_OUT_TEMP_lut_out = data_in & CNT1 $ !A1L81 # !data_in & A1L61 & CNT1 $ !A1L81;
POS_OUT_TEMP = DFFEAS(POS_OUT_TEMP_lut_out, clk, VCC, , , , , , );


--NEG_OUT_TEMP is NEG_OUT_TEMP
--operation mode is normal

NEG_OUT_TEMP_lut_out = data_in & CNT1 $ A1L81 # !data_in & A1L61 & CNT1 $ A1L81;
NEG_OUT_TEMP = DFFEAS(NEG_OUT_TEMP_lut_out, clk, VCC, , , , , , );


--A1L81 is POS_OUT_TEMP~106
--operation mode is normal

A1L81 = data_in & FLAG # !data_in & A1L61 & !A1L13;


--clk is clk
--operation mode is input

clk = INPUT();


--data_in is data_in
--operation mode is input

data_in = INPUT();


--pos_out is pos_out
--operation mode is output

pos_out = OUTPUT(A1L91Q);


--neg_out is neg_out
--operation mode is output

neg_out = OUTPUT(A1L31Q);