hdb3decoder.tan.rpt

基于VHDL语言的HDB3码编译码器的设计 HDB3 码的全称是三阶高密度双极性码

; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SEQUENCE[2] ; SEQUENCE[0] ; CLK        ; CLK      ; None                        ; None                      ; 1.814 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SEQUENCE[1] ; SEQUENCE[3] ; CLK        ; CLK      ; None                        ; None                      ; 1.699 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SEQUENCE[1] ; SEQUENCE[0] ; CLK        ; CLK      ; None                        ; None                      ; 1.545 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; NEG_FLAG    ; NEG_FLAG    ; CLK        ; CLK      ; None                        ; None                      ; 1.266 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SEQUENCE[1] ; SEQUENCE[2] ; CLK        ; CLK      ; None                        ; None                      ; 1.246 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SEQUENCE[0] ; SEQUENCE[3] ; CLK        ; CLK      ; None                        ; None                      ; 1.043 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SEQUENCE[2] ; SEQUENCE[3] ; CLK        ; CLK      ; None                        ; None                      ; 0.836 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SEQUENCE[0] ; SEQUENCE[1] ; CLK        ; CLK      ; None                        ; None                      ; 0.639 ns                ;
+-------+------------------------------------------------+-------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------+
; tsu                                                                ;
+-------+--------------+------------+--------+------------+----------+
; Slack ; Required tsu ; Actual tsu ; From   ; To         ; To Clock ;
+-------+--------------+------------+--------+------------+----------+
; N/A   ; None         ; 4.247 ns   ; NEG_IN ; NEG_IN_TMP ; CLK      ;
; N/A   ; None         ; 3.856 ns   ; POS_IN ; POS_IN_TMP ; CLK      ;
+-------+--------------+------------+--------+------------+----------+


+-----------------------------------------------------------------+
; tco                                                             ;
+-------+--------------+------------+----------+-----+------------+
; Slack ; Required tco ; Actual tco ; From     ; To  ; From Clock ;
+-------+--------------+------------+----------+-----+------------+
; N/A   ; None         ; 6.225 ns   ; NRZ~reg0 ; NRZ ; CLK        ;
+-------+--------------+------------+----------+-----+------------+


+--------------------------------------------------------------------------+
; th                                                                       ;
+---------------+-------------+-----------+--------+------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To         ; To Clock ;
+---------------+-------------+-----------+--------+------------+----------+
; N/A           ; None        ; -3.804 ns ; POS_IN ; POS_IN_TMP ; CLK      ;
; N/A           ; None        ; -4.195 ns ; NEG_IN ; NEG_IN_TMP ; CLK      ;
+---------------+-------------+-----------+--------+------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Fri Jul 15 01:36:01 2005
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off HDB3DECODER -c HDB3DECODER --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 164.31 MHz between source register "NEG_IN_TMP" and destination register "SEQUENCE[3]" (period= 6.086 ns)
    Info: + Longest register to register delay is 2.782 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y3_N4; Fanout = 6; REG Node = 'NEG_IN_TMP'
        Info: 2: + IC(0.527 ns) + CELL(0.442 ns) = 0.969 ns; Loc. = LC_X2_Y3_N5; Fanout = 1; COMB Node = 'SEQUENCE~611'
        Info: 3: + IC(1.075 ns) + CELL(0.738 ns) = 2.782 ns; Loc. = LC_X1_Y3_N5; Fanout = 2; REG Node = 'SEQUENCE[3]'
        Info: Total cell delay = 1.180 ns ( 42.42 % )
        Info: Total interconnect delay = 1.602 ns ( 57.58 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 2.730 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'CLK'
            Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X1_Y3_N5; Fanout = 2; REG Node = 'SEQUENCE[3]'
            Info: Total cell delay = 2.180 ns ( 79.85 % )
            Info: Total interconnect delay = 0.550 ns ( 20.15 % )
        Info: - Longest clock path from clock "CLK" to source register is 2.730 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'CLK'
            Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X2_Y3_N4; Fanout = 6; REG Node = 'NEG_IN_TMP'
            Info: Total cell delay = 2.180 ns ( 79.85 % )
            Info: Total interconnect delay = 0.550 ns ( 20.15 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: tsu for register "NEG_IN_TMP" (data pin = "NEG_IN", clock pin = "CLK") is 4.247 ns
    Info: + Longest pin to register delay is 6.940 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_33; Fanout = 1; PIN Node = 'NEG_IN'
        Info: 2: + IC(5.356 ns) + CELL(0.115 ns) = 6.940 ns; Loc. = LC_X2_Y3_N4; Fanout = 6; REG Node = 'NEG_IN_TMP'
        Info: Total cell delay = 1.584 ns ( 22.82 % )
        Info: Total interconnect delay = 5.356 ns ( 77.18 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.730 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'CLK'
        Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X2_Y3_N4; Fanout = 6; REG Node = 'NEG_IN_TMP'
        Info: Total cell delay = 2.180 ns ( 79.85 % )
        Info: Total interconnect delay = 0.550 ns ( 20.15 % )
Info: tco from clock "CLK" to destination pin "NRZ" through register "NRZ~reg0" is 6.225 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.730 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'CLK'
        Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X1_Y3_N8; Fanout = 1; REG Node = 'NRZ~reg0'
        Info: Total cell delay = 2.180 ns ( 79.85 % )
        Info: Total interconnect delay = 0.550 ns ( 20.15 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.271 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y3_N8; Fanout = 1; REG Node = 'NRZ~reg0'
        Info: 2: + IC(1.147 ns) + CELL(2.124 ns) = 3.271 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'NRZ'
        Info: Total cell delay = 2.124 ns ( 64.93 % )
        Info: Total interconnect delay = 1.147 ns ( 35.07 % )
Info: th for register "POS_IN_TMP" (data pin = "POS_IN", clock pin = "CLK") is -3.804 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.730 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 9; CLK Node = 'CLK'
        Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X2_Y3_N5; Fanout = 6; REG Node = 'POS_IN_TMP'
        Info: Total cell delay = 2.180 ns ( 79.85 % )
        Info: Total interconnect delay = 0.550 ns ( 20.15 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 6.549 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_32; Fanout = 1; PIN Node = 'POS_IN'
        Info: 2: + IC(4.965 ns) + CELL(0.115 ns) = 6.549 ns; Loc. = LC_X2_Y3_N5; Fanout = 6; REG Node = 'POS_IN_TMP'
        Info: Total cell delay = 1.584 ns ( 24.19 % )
        Info: Total interconnect delay = 4.965 ns ( 75.81 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Jul 15 01:36:02 2005
    Info: Elapsed time: 00:00:01