hdb3decoder.tan.rpt

基于VHDL语言的HDB3码编译码器的设计 HDB3 码的全称是三阶高密度双极性码

Timing Analyzer report for HDB3DECODER
Fri Jul 15 01:36:02 2005
Version 4.2 Build 157 12/07/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'CLK'
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                   ;
+------------------------------+-------+---------------+----------------------------------+------------+-------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From       ; To          ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+------------+-------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 4.247 ns                         ; NEG_IN     ; NEG_IN_TMP  ;            ; CLK      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 6.225 ns                         ; NRZ~reg0   ; NRZ         ; CLK        ;          ; 0            ;
; Worst-case th                ; N/A   ; None          ; -3.804 ns                        ; POS_IN     ; POS_IN_TMP  ;            ; CLK      ; 0            ;
; Clock Setup: 'CLK'           ; N/A   ; None          ; 164.31 MHz ( period = 6.086 ns ) ; NEG_IN_TMP ; SEQUENCE[3] ; CLK        ; CLK      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;            ;             ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+------------+-------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; CLK             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                             ;
+-------+------------------------------------------------+-------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From        ; To          ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 164.31 MHz ( period = 6.086 ns )               ; NEG_IN_TMP  ; SEQUENCE[3] ; CLK        ; CLK      ; None                        ; None                      ; 2.782 ns                ;
; N/A   ; 192.98 MHz ( period = 5.182 ns )               ; POS_IN_TMP  ; SEQUENCE[0] ; CLK        ; CLK      ; None                        ; None                      ; 2.330 ns                ;
; N/A   ; 203.92 MHz ( period = 4.904 ns )               ; POS_IN_TMP  ; SEQUENCE[3] ; CLK        ; CLK      ; None                        ; None                      ; 2.191 ns                ;
; N/A   ; 205.17 MHz ( period = 4.874 ns )               ; NEG_IN_TMP  ; POS_FLAG    ; CLK        ; CLK      ; None                        ; None                      ; 2.176 ns                ;
; N/A   ; 222.92 MHz ( period = 4.486 ns )               ; POS_IN_TMP  ; POS_FLAG    ; CLK        ; CLK      ; None                        ; None                      ; 1.982 ns                ;
; N/A   ; 250.25 MHz ( period = 3.996 ns )               ; NEG_IN_TMP  ; SEQUENCE[0] ; CLK        ; CLK      ; None                        ; None                      ; 1.737 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; NEG_IN_TMP  ; NEG_FLAG    ; CLK        ; CLK      ; None                        ; None                      ; 1.363 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; POS_FLAG    ; SEQUENCE[3] ; CLK        ; CLK      ; None                        ; None                      ; 2.939 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; POS_IN_TMP  ; NEG_FLAG    ; CLK        ; CLK      ; None                        ; None                      ; 1.265 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; NEG_FLAG    ; SEQUENCE[3] ; CLK        ; CLK      ; None                        ; None                      ; 2.688 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SEQUENCE[3] ; SEQUENCE[0] ; CLK        ; CLK      ; None                        ; None                      ; 2.544 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; POS_FLAG    ; SEQUENCE[0] ; CLK        ; CLK      ; None                        ; None                      ; 2.487 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; NEG_FLAG    ; SEQUENCE[0] ; CLK        ; CLK      ; None                        ; None                      ; 2.234 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SEQUENCE[0] ; SEQUENCE[0] ; CLK        ; CLK      ; None                        ; None                      ; 2.133 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; SEQUENCE[3] ; NRZ~reg0    ; CLK        ; CLK      ; None                        ; None                      ; 0.914 ns                ;