📄 71x_init.s
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;* History:
;* 01/01/2004 : V1.2
;* 14/07/2004 : V1.3
;******************************************************************************/
PRESERVE8
AREA Init, CODE, READONLY
;*******************************************************************************/
; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UNDEF EQU 0x1B
Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
; --- System memory locations
RAM_Base EQU 0x20000000
RAM_Limit EQU 0x20001000
SRAM_Base EQU 0x60000000
Stack_Base EQU RAM_Limit
SVC_Stack_Length EQU 256
IRQ_Stack_Length EQU 1024
USR_Stack_Length EQU 1024
FIQ_Stack_Length EQU 256
ABT_Stack_Length EQU 256
UNDEF_Stack_Length EQU 256
SVC_Stack EQU Stack_Base ; SVC stack
IRQ_Stack EQU SVC_Stack-SVC_Stack_Length ; followed by IRQ stack
USR_Stack EQU IRQ_Stack-IRQ_Stack_Length ; followed by USR stack
FIQ_Stack EQU USR_Stack-USR_Stack_Length ; followed by FIQ stack
ABT_Stack EQU FIQ_Stack-FIQ_Stack_Length ; followed by ABT stack
UNDEF_Stack EQU ABT_Stack-ABT_Stack_Length ; followed by UNDEF stack
; add by lilian to access EIC
EIC_Base_addr EQU 0xFFFFF800; EIC base address
ICR_off_addr EQU 0x00 ; Interrupt Control register offset
CIPR_off_addr EQU 0x08 ; Current Interrupt Priority Register offset
IVR_off_addr EQU 0x18 ; Interrupt Vector Register offset
FIR_off_addr EQU 0x1C ; Fast Interrupt Register offset
IER_off_addr EQU 0x20 ; Interrupt Enable Register offset
IPR_off_addr EQU 0x40 ; Interrupt Pending Bit Register offset
SIR0_off_addr EQU 0x60 ; Source Interrupt Register 0
EMI_Base_addr EQU 0x6C000000; EMI base address
BCON0_off_addr EQU 0x00 ; Bank 0 configuration register offset
BCON1_off_addr EQU 0x04 ; Bank 1 configuration register offset
BCON2_off_addr EQU 0x08 ; Bank 2 configuration register offset
BCON3_off_addr EQU 0x0C ; Bank 3 configuration register offset
EMI_ENABLE EQU 0x8000
EMI_SIZE_16 EQU 0x0001
GPIO1_Base_addr EQU 0xE0004000; GPIO1 base address
PC0_off_addr EQU 0x00 ; Port Configuration Register 0 offset
PC1_off_addr EQU 0x04 ; Port Configuration Register 1 offset
GPIO2_Base_addr EQU 0xE0005000; GPIO2 base address
PC2_off_addr EQU 0x08 ; Port Configuration Register 2 offset
PD_off_addr EQU 0x0C ; Port Data Register offset
CPM_Base_addr EQU 0xA0000040; CPM Base Address
BOOTCR_off_addr EQU 0x10 ; CPM - Boot Configuration Register
FLASH_mask EQU 0x0000 ; to remap FLASH at 0x0
RAM_mask EQU 0x0002 ; to remap RAM at 0x0
EXTMEM_mask EQU 0x0003 ; to remap EXTMEM at 0x0
;|----------------------------------------------------------------------------------|
;| - APB Bridge (System Peripheral) |
;|----------------------------------------------------------------------------------|
APB1_base_addr EQU 0xC0000000 ; APB Bridge1 Base Address
APB2_base_addr EQU 0xE0000000 ; APB Bridge2 Base Address
CKDIS_off_addr EQU 0x10 ; APB Bridge1 - Clock Disable Register
SWRES_off_addr EQU 0x14 ; APB Bridge1 - Software Reset Register
CKDIS1_config_all EQU 0x27FB ; To enable/disable clock of all APB1's peripherals
SWRES1_config_all EQU 0x27FB ; To reset all APB1's peripherals
CKDIS2_config_all EQU 0x7FDD ; To enable/disable clock of all APB2's peripherals
SWRES2_config_all EQU 0x7FDD ; To reset all APB2's peripherals
;*******************************************************************************
;|----------------------------------------------------------------------------------|
;| ---> User code address |
;|----------------------------------------------------------------------------------|
Flash_Program EQU 0x40004000
;*******************************************************************************
;* Macro Name : EIC_INIT
;* Description : This macro Initialize the EIC as following :
; - IRQ disabled
; - FIQ disabled
; - IVR contain the load PC opcode (0xF59FF00)
; - Current priority level equal to 0
; - All channels are disabled
; - All channels priority equal to 0
; - All SIR registers contain offset to the related IRQ
; table entry
;* Input : None.
;* Output : None.
;*******************************************************************************
MACRO
EIC_INIT
LDR r3, =EIC_Base_addr
MOV r0, #0
MVN r1, #0
MOV r2, #0x0c
STR r0, [r3, #ICR_off_addr]
STR r0, [r3, #IER_off_addr]
STR r1, [r3, #IPR_off_addr]
STR r2, [r3, #FIR_off_addr]
STR r0, [r3, #CIPR_off_addr]
LDR r4, =0xE59F0000
STR r4, [r3, #IVR_off_addr]; Write the LDR pc,[pc,#offset]
; instruction code in IVR[31:16]
LDR r2, =32 ; 32 Channel to initialize
LDR r0, =T0TIMI_Addr ; Read the address of the IRQs
; address table
LDR r1, =0x00000FFF
AND r0,r0,r1
LDR r5, =SIR0_off_addr ; Read SIR0 address
SUB r4,r0,#8 ; subtract 8 for prefetch
LDR r1, =0xF7E8 ; add the offset to the 0x00000000
; address(IVR address + 7E8 = 0x00000000)
; 0xF7E8 used to complete the
; LDR pc,[pc,#offset] opcode
ADD r1,r4,r1 ; compute the jump offset
EIC_INI MOV r4, r1, LSL #16 ; Left shift the result
STR r4, [r3, r5] ; Store the result in SIRx register
ADD r1, r1, #4 ; Next IRQ address
ADD r5, r5, #4 ; Next SIR
SUBS r2, r2, #1 ; Decrement the number of SIR registers
; to initialize
BNE EIC_INI ; If more then continue
MEND
;---------------------------------------------------------------
; ?program_start
;---------------------------------------------------------------
; MODULE ?program_start
; RSEG IRQ_STACK:DATA(2)
; RSEG FIQ_STACK:DATA(2)
; RSEG UND_STACK:DATA(2)
; RSEG ABT_STACK:DATA(2)
; RSEG SVC_STACK:DATA(2)
; RSEG CSTACK:DATA(2)
; RSEG ICODE:CODE(2)
; PUBLIC __program_start
; EXTERN ?main
; CODE32
; define remapping
; If you need to remap memory before entring the main program
; uncomment next ligne
GBLL remapping
; Then define which memory to remap to address 0x00000000
; Uncomment next line if you want to remap RAM
; GBLL remap_ram
; Uncomment next line if you want to remap FLASH
GBLL remap_flash
ENTRY
EXPORT __program_start
IMPORT T0TIMI_Addr
__program_start
LDR pc, =NextInst
NextInst
NOP ; Wait for OSC stabilization
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MSR CPSR_c, #Mode_ABT|F_Bit|I_Bit
LDR SP, =ABT_Stack ;=SFE(ABT_STACK )& 0xFFFFFFF8
MSR CPSR_c, #Mode_UNDEF|F_Bit|I_Bit
LDR SP,= UNDEF_Stack ;= SFE(UND_STACK) & 0xFFFFFFF8
MSR CPSR_c, #Mode_SVC|F_Bit|I_Bit
LDR SP, =SVC_Stack ;=SFE(SVC_STACK) & 0xFFFFFFF8
; here add extra code for close interrupt : EIC->ICR=0 add by lilian
; LDR R0,=EIC_Base_addr ;=EIC_BASE
; LDR R1,=0x0
; STR R1,[R0]
EIC_INIT
;******************************************************************************
;REMAPPING
;Description : Remapping memory whether RAM,FLASH or External memory
; at Address 0x0 after the application has started executing.
; Remapping is generally done to allow RAM to replace FLASH
; or EXTMEM at 0x0.
; the remapping of RAM allow copying of vector table into RAM
;******************************************************************************
IF :DEF: remapping
IF :DEF: remap_flash
MOV r0, #FLASH_mask
ENDIF
IF :DEF: remap_ram
MOV r0, #RAM_mask
ENDIF
IF :DEF: remap_ext
MOV r0, #EXTMEM_mask
ENDIF
LDR r1, =CPM_Base_addr
LDRH r2, [r1, #BOOTCR_off_addr]; Read BOOTCR Register
BIC r2, r2, #0x03 ; Reset the two LSB bits of BOOTCR
ORR r2, r2, r0 ; change the two LSB bits of BOOTCR
STRH r2, [r1, #BOOTCR_off_addr]; Write BOOTCR Register
ENDIF
MSR CPSR_c, #Mode_FIQ|I_Bit; Change to FIQ mode
LDR SP, =FIQ_Stack ;=SFE(FIQ_STACK)& 0xFFFFFFF8 ; Initialize FIQ stack pointer
MSR CPSR_c, #Mode_IRQ|I_Bit; Change to IRQ mode
LDR SP, =IRQ_Stack ;=SFE(IRQ_STACK)& 0xFFFFFFF8 ; Initialize IRQ stack pointer
MSR CPSR_c, #Mode_USR ; Change to User mode, Enable IRQ and FIQ
LDR SP, =USR_Stack ;=CSTACK ;=SFE(CSTACK) & 0xFFFFFFF8 ; Initialize USR stack pointer
;******************************************************************************
; ---> Test if SEL button is pushed (P1.8 Low)
;******************************************************************************
LDR r0, =GPIO1_Base_addr ; configure P1.8 as Input TTL
LDR r1, =0x100
STR r1, [r0, #PC0_off_addr]
LDR r1, =0x0
STR r1, [r0, #PC1_off_addr]
STR r1, [r0, #PC2_off_addr]
LDR r1, [r0, #PD_off_addr]
ANDS r1, r1, #0x00000100
BNE NextSector ; Branch to the user code
; --- Now branches to a C lib function that copies RO data from their
; load region to their execute region, create the RW and ZI regions
; then jumps to user C main program.
IMPORT Main
; --- Now branches to a C lib function that copies RO data from their
; load region to their execute region, create the RW and ZI regions
; then jumps to user C main program.
B Main ; Note : use B not BL, because an application will
; never return this wayNextSector
NextSector
LDR pc, =Flash_Program
LTORG
END
;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****
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