dm9000x.c

2410 U-BOOT的dm9000网卡驱动

		    	bd->bi_enetaddr[2], bd->bi_enetaddr[3],
	        	bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
		
		for (i = 0; i < 6; i++)
			DM9000_iow(0x10 + i, bd->bi_enetaddr[i]);
		
		for (i = 0; i < 8; i++)
			DM9000_iow(0x16 + i, 0x00);
			DM9000_iow(0x1d, 0x80);
	
		/* Activate DM9000 */
		//majesticccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc
		//DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);	/* RX enable */
		DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_RXEN);	/* RX enable */
		DM9000_iow(DM9000_IMR, IMR_PAR);	/* Enable TX/RX interrupt mask */
		
		i = 0;
		while (!(phy_read(1) & 0x04)) {	/* autonegation complete bit */
			udelay(1000);
			i++;
			if (i == 30000) {
				
				printf("\n\n");
				printf("could not establish link\n");
				
				return (0);
			}
		}
		
		udelay(1000);
		//majesticcccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc

		/* see what we've got */
		lnk = DM9000_ior(0x00) & 0x08;//majesticccccccccccccccccccccccccccccccccccccccccccc
		lnk |= DM9000_ior(0x01) & 0x80;//majesticcccccccccccccccccccccccccccccccccccccccccc
		printf("\n operating at ");
		switch (lnk) {
		case 0x80:
			printf("10M half duplex ");
			break;
		case 0x88:
			printf("10M full duplex ");
			break;
		case 0x00:
			printf("100M half duplex ");
			break;
		case 0x08:
			printf("100M full duplex ");
			break;
		}
		printf("mode\n");
		
		return(0);
	}
	else
	{
		return(-1);//majesticccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc
	}
}

/*
  Hardware start transmission.
  Send a packet to media from the upper layer.
*/
int
eth_send(volatile void *packet, int length)
{
	char *data_ptr;
	u32 tmplen, i;
	int tmo;
	DM9000_DBG("eth_send: length: %d\n", length);
	for (i = 0; i < length; i++) {
		if (i % 16 == 0)//majesticccccccccccccccccccccccccccccccccccccccccccccccccccccccc
			DM9000_DBG("\nSend: %02x: ", i);
		DM9000_DBG("%02x ", ((unsigned char *) packet)[i]);
	} DM9000_DBG("\n");
	
	
	/* Move data to DM9000 TX RAM */
	data_ptr = (char *) packet;
	DM9000_outb(DM9000_MWCMD, DM9000_IO);

#ifdef CONFIG_DM9000_USE_8BIT
	/* Byte mode */
	for (i = 0; i < length; i++)
		DM9000_outb((data_ptr[i] & 0xff), DM9000_DATA);

#endif				/*  */
#ifdef CONFIG_DM9000_USE_16BIT
	tmplen = (length + 1) / 2;
	for (i = 0; i < tmplen; i++)
		DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);

#endif				/*  */
#ifdef CONFIG_DM9000_USE_32BIT
	tmplen = (length + 3) / 4;
	for (i = 0; i < tmplen; i++)
		DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);

#endif				/*  */

	/* Set TX length to DM9000 */
	DM9000_iow(DM9000_TXPLL, length & 0xff);
	DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);

	/* Issue TX polling command */
	DM9000_iow(DM9000_TCR, TCR_TXREQ);	/* Cleared after TX complete */

	/* wait for end of transmission */
	tmo = get_timer(0) + 5 * CFG_HZ;
	while (DM9000_ior(DM9000_TCR) & TCR_TXREQ) {
		if (get_timer(0) >= tmo) {
			printf("transmission timeout\n");
			break;
		}
	}
	DM9000_DBG("transmit done\n\n");
	return 0;
}

/*
  Stop the interface.
  The interface is stopped when it is brought.
*/
void
eth_halt(void)
{
	DM9000_DBG("eth_halt\n");

	/* RESET devie */
	phy_write(0, 0x8000);	/* PHY RESET */
	DM9000_iow(DM9000_GPR, 0x01);	/* Power-Down PHY */
	DM9000_iow(DM9000_IMR, 0x80);	/* Disable all interrupt */
	DM9000_iow(DM9000_RCR, 0x00);	/* Disable RX */
}

/*
  Received a packet and pass to upper layer
*/
int
eth_rx(void)
{
	u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
	u16 RxStatus, RxLen = 0;
	u32 tmplen, i;
	
//majesticcccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc	
	if((DM9000_ior(0xfe) & 0x01) != 0x01) 
	{
		//printf("no packet reg 0xfe 0x%02x \n", DM9000_ior(0xfe));
     	//printf("reg 0x05 0x%02x \n", DM9000_ior(0x05));
		return (0); 
	}
	
	//printf("\n");
	//printf("reg 0x05 0x%02x \n", DM9000_ior(0x05));
	//printf("reg 0x38 0x%02x \n", DM9000_ior(0x38));
	//printf("reg MRR  0x%02x%02x \n", DM9000_ior(0xf5),DM9000_ior(0xf4));
	//printf("reg 0xfe 0x%02x \n", DM9000_ior(0xfe));
	//printf("reg 0xff 0x%02x \n", DM9000_ior(0xff));
	
//majesticccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc
	/* Check packet ready or not */
	DM9000_ior(DM9000_MRCMDX);	/* Dummy read */
	DM9000_ior(0xfe);	/* Dummy read */
	rxbyte = DM9000_ior(DM9000_MRCMDX);	/* Got most updated data */
	if (rxbyte == 0)
	{
		DM9000_iow(0xfe, 0x01);
		return 0;
	}
//majesticccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc	

	/* Status check: this byte must be 0 or 1 */
	if (rxbyte > 1) {
		DM9000_iow(DM9000_RCR, 0x00);	/* Stop Device */
		DM9000_iow(DM9000_ISR, 0x80);	/* Stop INT request */
		DM9000_DBG("rx status check: %d\n", rxbyte);
	}
	DM9000_DBG("receiving packet\n");

	/* A packet ready now  & Get status/length */
	DM9000_outb(DM9000_MRCMD, DM9000_IO);

#ifdef CONFIG_DM9000_USE_8BIT
	RxStatus = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8);
	RxLen = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8);

#endif				/*  */
#ifdef CONFIG_DM9000_USE_16BIT
	RxStatus = DM9000_inw(DM9000_DATA);
	RxLen = DM9000_inw(DM9000_DATA);
#endif				/*  */
#ifdef CONFIG_DM9000_USE_32BIT
	tmpdata = DM9000_inl(DM9000_DATA);
	RxStatus = tmpdata;
	RxLen = tmpdata >> 16;
#endif				/*  */
	DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);

#if 0	
	printf("\n\n");
	printf("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
	printf("reg MRR  0x%02x%02x \n", DM9000_ior(0xf5),DM9000_ior(0xf4));
	
	DM9000_outb(DM9000_MRCMD, DM9000_IO);
	printf("\n\n");
#endif 
//majesticccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc

	/* Move data from DM9000 */
	/* Read received packet from RX SRAM */
#ifdef CONFIG_DM9000_USE_8BIT
	for (i = 0; i < RxLen; i++)
		rdptr[i] = DM9000_inb(DM9000_DATA);

#endif				/*  */
#ifdef CONFIG_DM9000_USE_16BIT
	tmplen = (RxLen + 1) / 2;
	for (i = 0; i < tmplen; i++)
		((u16 *) rdptr)[i] = DM9000_inw(DM9000_DATA);

#endif				/*  */
#ifdef CONFIG_DM9000_USE_32BIT
	tmplen = (RxLen + 3) / 4;
	for (i = 0; i < tmplen; i++)
		((u32 *) rdptr)[i] = DM9000_inl(DM9000_DATA);

#endif				/*  */
	if ((RxStatus & 0xbf00) || (RxLen < 0x40)
	    || (RxLen > DM9000_PKT_MAX)) {
		if (RxStatus & 0x100) {
			printf("rx fifo error\n");
		}
		if (RxStatus & 0x200) {
			printf("rx crc error\n");
		}
		if (RxStatus & 0x8000) {
			printf("rx length error\n");
		}
		if (RxLen > DM9000_PKT_MAX) {
			printf("rx length too big\n");
			dm9000_reset();
		}
	} else {

		/* Pass to upper layer */
		DM9000_DBG("passing packet to upper layer\n");
		NetReceive(NetRxPackets[0], RxLen);
		return RxLen;
	}
	return 0;
}

/*void DM9000_get_enetaddr (uchar * addr)
{
	int i;
	u8 temp;
	
	printf ("\n\n set Ethernet MAC: ");
    for (i = 0; i <6; i++) 
    {
      temp = i * 0x11;
      *addr++ = temp;
      printf ("%x:", temp);
    }
    
	printf ("\n\n ");
	
	return;
}
*/

/*
  Read a word data from SROM
*/
#if 0
static u16
read_srom_word(int offset)
{
	DM9000_iow(DM9000_EPAR, offset);
	DM9000_iow(DM9000_EPCR, 0x4);
	do
	{
		udelay(200);
	}while(DM9000_ior(DM9000_EPCR) & 0x01);
	DM9000_iow(DM9000_EPCR, 0x0);
	return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8));
}
#endif
/*
   Read a byte from I/O port
*/
static u8
DM9000_ior(int reg)
{
	DM9000_outb(reg, DM9000_IO);
	return DM9000_inb(DM9000_DATA);
}

/*
   Write a byte to I/O port
*/
static void
DM9000_iow(int reg, u8 value)
{
	DM9000_outb(reg, DM9000_IO);
	DM9000_outb(value, DM9000_DATA);
}

/*
   Read a word from phyxcer
*/
static u16
phy_read(int reg)
{
	u16 val;

	/* Fill the phyxcer register into REG_0C */
	DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
	DM9000_iow(DM9000_EPCR, 0xc);	/* Issue phyxcer read command */
//majesticccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc	
	do
	{
		udelay(200);                /* Wait read complete */
	}while(DM9000_ior(DM9000_EPCR) & 0x01);
//majesticccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc	
	DM9000_iow(DM9000_EPCR, 0x0);	/* Clear phyxcer read command */
	val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);

	/* The read data keeps on REG_0D & REG_0E */
	DM9000_DBG("phy_read(%d): %d\n", reg, val);
	return val;
}

/*
   Write a word to phyxcer
*/
static void
phy_write(int reg, u16 value)
{

	/* Fill the phyxcer register into REG_0C */
	DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);

	/* Fill the written data into REG_0D & REG_0E */
	DM9000_iow(DM9000_EPDRL, (value & 0xff));
	DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
	DM9000_iow(DM9000_EPCR, 0xa);	/* Issue phyxcer write command */
//majesticccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc	
	do
	{
		udelay(500);                /* Wait read complete */
	}while(DM9000_ior(DM9000_EPCR) & 0x01);
//majesticccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc	
	DM9000_iow(DM9000_EPCR, 0x0);	/* Clear phyxcer write command */
	DM9000_DBG("phy_write(reg:%d, value:%d)\n", reg, value);
}
#endif				/* CONFIG_DRIVER_DM9000 */