msp430x14x.h

采用MPS430控制的项目

#define P2OUT_              (0x0029)  /* Port 2 Output */
DEFC(    P2OUT             , P2OUT_)
#define P2DIR_              (0x002A)  /* Port 2 Direction */
DEFC(    P2DIR             , P2DIR_)
#define P2IFG_              (0x002B)  /* Port 2 Interrupt Flag */
DEFC(    P2IFG             , P2IFG_)
#define P2IES_              (0x002C)  /* Port 2 Interrupt Edge Select */
DEFC(    P2IES             , P2IES_)
#define P2IE_               (0x002D)  /* Port 2 Interrupt Enable */
DEFC(    P2IE              , P2IE_)
#define P2SEL_              (0x002E)  /* Port 2 Selection */
DEFC(    P2SEL             , P2SEL_)

/************************************************************
* DIGITAL I/O Port3/4
************************************************************/

#define P3IN_               (0x0018)  /* Port 3 Input */
READ_ONLY DEFC( P3IN           , P3IN_)
#define P3OUT_              (0x0019)  /* Port 3 Output */
DEFC(    P3OUT             , P3OUT_)
#define P3DIR_              (0x001A)  /* Port 3 Direction */
DEFC(    P3DIR             , P3DIR_)
#define P3SEL_              (0x001B)  /* Port 3 Selection */
DEFC(    P3SEL             , P3SEL_)

#define P4IN_               (0x001C)  /* Port 4 Input */
READ_ONLY DEFC( P4IN           , P4IN_)
#define P4OUT_              (0x001D)  /* Port 4 Output */
DEFC(    P4OUT             , P4OUT_)
#define P4DIR_              (0x001E)  /* Port 4 Direction */
DEFC(    P4DIR             , P4DIR_)
#define P4SEL_              (0x001F)  /* Port 4 Selection */
DEFC(    P4SEL             , P4SEL_)

/************************************************************
* DIGITAL I/O Port5/6
************************************************************/

#define P5IN_               (0x0030)  /* Port 5 Input */
READ_ONLY DEFC( P5IN           , P5IN_)
#define P5OUT_              (0x0031)  /* Port 5 Output */
DEFC(    P5OUT             , P5OUT_)
#define P5DIR_              (0x0032)  /* Port 5 Direction */
DEFC(    P5DIR             , P5DIR_)
#define P5SEL_              (0x0033)  /* Port 5 Selection */
DEFC(    P5SEL             , P5SEL_)

#define P6IN_               (0x0034)  /* Port 6 Input */
READ_ONLY DEFC( P6IN           , P6IN_)
#define P6OUT_              (0x0035)  /* Port 6 Output */
DEFC(    P6OUT             , P6OUT_)
#define P6DIR_              (0x0036)  /* Port 6 Direction */
DEFC(    P6DIR             , P6DIR_)
#define P6SEL_              (0x0037)  /* Port 6 Selection */
DEFC(    P6SEL             , P6SEL_)

/************************************************************
* USART
************************************************************/

#define PENA                (0x80)        /* UCTL */
#define PEV                 (0x40)
#define SPB                 (0x20)        /* to distinguish from stackpointer SP */
#define CHAR                (0x10)
#define LISTEN              (0x08)
#define SYNC                (0x04)
#define MM                  (0x02)
#define SWRST               (0x01)

#define CKPH                (0x80)        /* UTCTL */
#define CKPL                (0x40)
#define SSEL1               (0x20)
#define SSEL0               (0x10)
#define URXSE               (0x08)
#define TXWAKE              (0x04)
#define STC                 (0x02)
#define TXEPT               (0x01)

#define FE                  (0x80)        /* URCTL */
#define PE                  (0x40)
#define OE                  (0x20)
#define BRK                 (0x10)
#define URXEIE              (0x08)
#define URXWIE              (0x04)
#define RXWAKE              (0x02)
#define RXERR               (0x01)

/************************************************************
* USART 0
************************************************************/

#define U0CTL_              (0x0070)  /* USART 0 Control */
DEFC(    U0CTL             , U0CTL_)
#define U0TCTL_             (0x0071)  /* USART 0 Transmit Control */
DEFC(    U0TCTL            , U0TCTL_)
#define U0RCTL_             (0x0072)  /* USART 0 Receive Control */
DEFC(    U0RCTL            , U0RCTL_)
#define U0MCTL_             (0x0073)  /* USART 0 Modulation Control */
DEFC(    U0MCTL            , U0MCTL_)
#define U0BR0_              (0x0074)  /* USART 0 Baud Rate 0 */
DEFC(    U0BR0             , U0BR0_)
#define U0BR1_              (0x0075)  /* USART 0 Baud Rate 1 */
DEFC(    U0BR1             , U0BR1_)
#define U0RXBUF_            (0x0076)  /* USART 0 Receive Buffer */
READ_ONLY DEFC( U0RXBUF        , U0RXBUF_)
#define U0TXBUF_            (0x0077)  /* USART 0 Transmit Buffer */
DEFC(    U0TXBUF           , U0TXBUF_)

/* Alternate register names */

#define UCTL0_              U0CTL_    /* USART 0 Control */
DEFC(    UCTL0             , UCTL0_)
#define UTCTL0_             U0TCTL_   /* USART 0 Transmit Control */
DEFC(    UTCTL0            , UTCTL0_)
#define URCTL0_             U0RCTL_   /* USART 0 Receive Control */
DEFC(    URCTL0            , URCTL0_)
#define UMCTL0_             U0MCTL_   /* USART 0 Modulation Control */
DEFC(    UMCTL0            , UMCTL0_)
#define UBR00_              U0BR0_    /* USART 0 Baud Rate 0 */
DEFC(    UBR00             , UBR00_)
#define UBR10_              U0BR1_    /* USART 0 Baud Rate 1 */
DEFC(    UBR10             , UBR10_)
#define RXBUF0_             U0RXBUF_  /* USART 0 Receive Buffer */
READ_ONLY DEFC( RXBUF0         , RXBUF0_)
#define TXBUF0_             U0TXBUF_  /* USART 0 Transmit Buffer */
DEFC(    TXBUF0            , TXBUF0_)

#define UCTL_0_             U0CTL_    /* USART 0 Control */
DEFC(    UCTL_0            , UCTL_0_)
#define UTCTL_0_            U0TCTL_   /* USART 0 Transmit Control */
DEFC(    UTCTL_0           , UTCTL_0_)
#define URCTL_0_            U0RCTL_   /* USART 0 Receive Control */
DEFC(    URCTL_0           , URCTL_0_)
#define UMCTL_0_            U0MCTL_   /* USART 0 Modulation Control */
DEFC(    UMCTL_0           , UMCTL_0_)
#define UBR0_0_             U0BR0_    /* USART 0 Baud Rate 0 */
DEFC(    UBR0_0            , UBR0_0_)
#define UBR1_0_             U0BR1_    /* USART 0 Baud Rate 1 */
DEFC(    UBR1_0            , UBR1_0_)
#define RXBUF_0_            U0RXBUF_  /* USART 0 Receive Buffer */
READ_ONLY DEFC( RXBUF_0        , RXBUF_0_)
#define TXBUF_0_            U0TXBUF_  /* USART 0 Transmit Buffer */
DEFC(    TXBUF_0           , TXBUF_0_)

/************************************************************
* USART 1
************************************************************/

#define U1CTL_              (0x0078)  /* USART 1 Control */
DEFC(    U1CTL             , U1CTL_)
#define U1TCTL_             (0x0079)  /* USART 1 Transmit Control */
DEFC(    U1TCTL            , U1TCTL_)
#define U1RCTL_             (0x007A)  /* USART 1 Receive Control */
DEFC(    U1RCTL            , U1RCTL_)
#define U1MCTL_             (0x007B)  /* USART 1 Modulation Control */
DEFC(    U1MCTL            , U1MCTL_)
#define U1BR0_              (0x007C)  /* USART 1 Baud Rate 0 */
DEFC(    U1BR0             , U1BR0_)
#define U1BR1_              (0x007D)  /* USART 1 Baud Rate 1 */
DEFC(    U1BR1             , U1BR1_)
#define U1RXBUF_            (0x007E)  /* USART 1 Receive Buffer */
READ_ONLY DEFC( U1RXBUF        , U1RXBUF_)
#define U1TXBUF_            (0x007F)  /* USART 1 Transmit Buffer */
DEFC(    U1TXBUF           , U1TXBUF_)

/* Alternate register names */
#define UCTL1_              (U1CTL_)   /* USART 1 Control */
DEFC(    UCTL1             , UCTL1_)
#define UTCTL1_             (U1TCTL_)  /* USART 1 Transmit Control */
DEFC(    UTCTL1            , UTCTL1_)
#define URCTL1_             (U1RCTL_)  /* USART 1 Receive Control */
DEFC(    URCTL1            , URCTL1_)
#define UMCTL1_             (U1MCTL_)  /* USART 1 Modulation Control */
DEFC(    UMCTL1            , UMCTL1_)
#define UBR01_              (U1BR0_)   /* USART 1 Baud Rate 0 */
DEFC(    UBR01             , UBR01_)
#define UBR11_              (U1BR1_)   /* USART 1 Baud Rate 1 */
DEFC(    UBR11             , UBR11_)
#define RXBUF1_             (U1RXBUF_) /* USART 1 Receive Buffer */
READ_ONLY DEFC( RXBUF1         , RXBUF1_)
#define TXBUF1_             (U1TXBUF_) /* USART 1 Transmit Buffer */
DEFC(    TXBUF1            , TXBUF1_)

#/* Alternate register names */
#define UCTL_1_             (U1CTL_)    /* USART 1 Control */
DEFC(    UCTL_1            , UCTL_1_)
#define UTCTL_1_            (U1TCTL_)  /* USART 1 Transmit Control */
DEFC(    UTCTL_1           , UTCTL_1_)
#define URCTL_1_            (U1RCTL_)  /* USART 1 Receive Control */
DEFC(    URCTL_1           , URCTL_1_)
#define UMCTL_1_            (U1MCTL_)  /* USART 1 Modulation Control */
DEFC(    UMCTL_1           , UMCTL_1_)
#define UBR0_1_             (U1BR0_)   /* USART 1 Baud Rate 0 */
DEFC(    UBR0_1            , UBR0_1_)
#define UBR1_1_             (U1BR1_)   /* USART 1 Baud Rate 1 */
DEFC(    UBR1_1            , UBR1_1_)
#define RXBUF_1_            (U1RXBUF_) /* USART 1 Receive Buffer */
READ_ONLY DEFC( RXBUF_1        , RXBUF_1_)
#define TXBUF_1_            (U1TXBUF_) /* USART 1 Transmit Buffer */
DEFC(    TXBUF_1           , TXBUF_1_)

/************************************************************
* Timer A
************************************************************/

#define TAIV_               (0x012E)  /* Timer A Interrupt Vector Word */
READ_ONLY DEFW( TAIV           , TAIV_)
#define TACTL_              (0x0160)  /* Timer A Control */
DEFW(    TACTL             , TACTL_)
#define TACCTL0_            (0x0162)  /* Timer A Capture/Compare Control 0 */
DEFW(    TACCTL0           , TACCTL0_)
#define TACCTL1_            (0x0164)  /* Timer A Capture/Compare Control 1 */
DEFW(    TACCTL1           , TACCTL1_)
#define TACCTL2_            (0x0166)  /* Timer A Capture/Compare Control 2 */
DEFW(    TACCTL2           , TACCTL2_)
#define TAR_                (0x0170)  /* Timer A */
DEFW(    TAR               , TAR_)
#define TACCR0_             (0x0172)  /* Timer A Capture/Compare 0 */
DEFW(    TACCR0            , TACCR0_)
#define TACCR1_             (0x0174)  /* Timer A Capture/Compare 1 */
DEFW(    TACCR1            , TACCR1_)
#define TACCR2_             (0x0176)  /* Timer A Capture/Compare 2 */
DEFW(    TACCR2            , TACCR2_)

/* Alternate register names */
#define CCTL0_              TACCTL0_    /* Timer A Capture/Compare Control 0 */
DEFW(    CCTL0 , CCTL0_)
#define CCTL1_              TACCTL1_    /* Timer A Capture/Compare Control 1 */
DEFW(    CCTL1 , CCTL1_)
#define CCTL2_              TACCTL2_    /* Timer A Capture/Compare Control 2 */
DEFW(    CCTL2 , CCTL2_)
#define CCR0_               TACCR0_     /* Timer A Capture/Compare 0 */
DEFW(    CCR0 , CCR0_)
#define CCR1_               TACCR1_     /* Timer A Capture/Compare 1 */
DEFW(    CCR1 , CCR1_)
#define CCR2_               TACCR2_     /* Timer A Capture/Compare 2 */
DEFW(    CCR2 , CCR2_)

#define TASSEL2             (0x0400)  /* unused */        /* to distinguish from USART SSELx */
#define TASSEL1             (0x0200)  /* Timer A clock source select 0 */
#define TASSEL0             (0x0100)  /* Timer A clock source select 1 */
#define ID1                 (0x0080)  /* Timer A clock input devider 1 */
#define ID0                 (0x0040)  /* Timer A clock input devider 0 */
#define MC1                 (0x0020)  /* Timer A mode control 1 */
#define MC0                 (0x0010)  /* Timer A mode control 0 */
#define TACLR               (0x0004)  /* Timer A counter clear */
#define TAIE                (0x0002)  /* Timer A counter interrupt enable */
#define TAIFG               (0x0001)  /* Timer A counter interrupt flag */

#define MC_0                (0*0x10)  /* Timer A mode control: 0 - Stop */
#define MC_1                (1*0x10)  /* Timer A mode control: 1 - Up to CCR0 */
#define MC_2                (2*0x10)  /* Timer A mode control: 2 - Continous up */
#define MC_3                (3*0x10)  /* Timer A mode control: 3 - Up/Down */
#define ID_0                (0*0x40)  /* Timer A input divider: 0 - /1 */