📄 speak1.asm
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NAME SPEAK1.ASM
#include "..\Inc\msp430x14x.h"
RXD EQU 004h ; RXD on P1.2
TXD EQU 002h ; TXD on P1.1
; RAM Registers Used
RXTXData EQU 0200h ; Register for RX or TX UART Data
BitCnt EQU 0202h ; Register used to count UART bits
;
; Conditions for 2400 Baud SW UART, ACLK = 32768
Bitime_5 EQU 77h ; .5 bit length + small adjustment
Bitime EQU 0Ah ; 427us bit length ~ 2341 baud
;9784
; M.Buccini
; Texas Instruments, Inc
; March 2002
;*****************************************************************************
ORG 0f000h
;-----------------------------------------------------------------------------
PUBLIC RESET ;
RESET mov.w #300h,SP ; Initialize Stackpointer
;call #Init_Sys ; Initialize System Peripherals
PUBLIC Init_Sys
Init_Sys ; Subroutine to set-up peripherals
;-----------------------------------------------------------------------------
StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT
SetupTA mov.w #TASSEL1+ID1+ID0+MC1,&TACTL ; ACLK, continous mode
SetupC0 mov.w #OUT,&CCTL0 ; TXD Idle as Mark
SetupP1_2 bis.b #TXD,&P1SEL ; P1.1/TA0 for TXD function
bis.b #TXD,&P1DIR ; TXD output on P1
bis.b #RXD,&P1SEL ; P1.2/TA0 as RXD input
eint ; General Enable Interrupts
ret ;
;-----------------------------------------------------------------------------
; Subroutine that Transmit One Byte from RXTXData Buffer.
;-----------------------------------------------------------------------------
PUBLIC TX_Byte
;RSEG CODE
TX_Byte
mov.w R12,RXTXData
mov.w &TAR,&CCR0 ; Current state of TA Counter
add.w #Bitime,&CCR0 ; Some time till first bit
bis.w #0100h, &RXTXData ; Add mark stop bit to RXTXData
rla.w &RXTXData ; Add space start bit
mov.w #10,&BitCnt ; Load Bit Counter, 8 data + SP
mov.w #OUTMOD0+CCIE,&CCTL0 ; TXD = mark = idle
TX_Wait bit.w #CCIE,&CCTL0 ; Wait for TX completion
jnz TX_Wait ;
ret ;
;-----------------------------------------------------------------------------
PUBLIC TA0_ISR
TA0_ISR ; CCR0/UART ISR: RXTXData Buffer holds UART Data.
;-----------------------------------------------------------------------------
add.w #Bitime,&CCR0 ; Time to Next Bit
bit.w #CCIS0,&CCTL0 ; RX on ISCCIB?
jnz UART_RX ; Jump --> RX
UART_TX cmp.w #00h,&BitCnt ;
jne TX_Next ; Next bit?
bic.w #CCIE,&CCTL0 ; All Bits TX or RX, Disable Int.
ret ;
TX_Next bic.w #OUTMOD2,&CCTL0 ; TX Mark
rra.w &RXTXData ; LSB is shifted to carry
jc TX_Test ; Jump --> bit = 1
TX_Space bis.w #OUTMOD2,&CCTL0 ; TX Space
TX_Test dec.w &BitCnt ; All bits sent (or received)?
ret ;
;
UART_RX bit.w #CAP,&CCTL0 ; Compare mode for start bit edge
jz RX_Bit ; Start bit edge?
RX_Edge bic.w #CAP,&CCTL0 ; Switch to Compare mode
add.w #Bitime_5,&CCR0 ; First databit 1.5 bits from edge
ret ;
RX_Bit bit.w #SCCI,&CCTL0 ; Get bit waiting in receive latch
rrc.b &RXTXData ; Store received bit
RX_Test dec.w &BitCnt ; All bits sent (or received)?
jnz RX_Next ; Next bit?
;>>>>>>>>>> Decode of Received Byte Here <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
RX_Comp bic.w #CCIE,&CCTL0 ; All Bits RXed, Disable Interrupt
mov.w #GIE,0(SP) ; Decode Byte= Active in Mainloop
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
RX_Next ret ;
;
;-----------------------------------------------------------------------------
; Interrupt Vectors Used MSP430x11x1
;-----------------------------------------------------------------------------
; COMMON INTVEC(2)
; ORG RESET_VECTOR ; MSP430 RESET Vector
; DW RESET ;
; COMMON INTVEC(1)
; ORG TIMERA0_VECTOR ; Timer_A0 Vector
; DW TA0_ISR ;
END
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