int.lst

采用LPC935控制的一个项目

C51 COMPILER V7.10   INT                                                                   06/18/2007 11:05:53 PAGE 1   


C51 COMPILER V7.10, COMPILATION OF MODULE INT
OBJECT MODULE PLACED IN int.obj
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE source\int.c BROWSE DEBUG OBJECTEXTEND PRINT(.\int.lst) OBJECT(int.obj)

line level    source

   1          #include <REG935.H>
   2          #include"..\SOURCE\general.h"
   3          
   4          BYTE CONTRAST_ADD=0x01;
   5          BYTE CONTRAST=0x80;
   6          void cpuint(void)
   7          {
   8   1      
   9   1              //      BYTE i;
  10   1              //RSTSRC=0x32;          //内部复位
  11   1      
  12   1              //PT0AD=PT0AD&0xff;     
  13   1      
  14   1              P0M1=0x00;                      // 推挽输出        //准双向口
  15   1              P0M2=0x00;
  16   1      
  17   1              P1M1=0xae;                      //
  18   1              P1M2=0x5d;
  19   1      
  20   1              P2M1=0x33;                      //P2:0xcf,0x7e
  21   1              P2M2=0xcc;
  22   1              
  23   1              P3M1=0x00;                      //P3:0x03,0x00
  24   1              P3M2=0x03;
  25   1       
  26   1              POWCTRL=1;
  27   1      
  28   1              DIVM=0x00;//0分频
  29   1              //TRIM|=0xc0;   
  30   1              TMOD|=0x11;//16位方式 
  31   1              
  32   1              TH0=0x20;//28036/256;   
  33   1              TL0=0x03;//28036%256;
  34   1              
  35   1              TH1=0x8a;//35536/256
  36   1              TL1=0xd0;//35536%256
  37   1      
  38   1              SCON=0x50; //使能接收选择串口模式1
  39   1              SSTAT=0xE0; //选择独立的Tx/Rx 中断
  40   1              BRGR0=0xF0; //9600 baud @ 7.373MHz
  41   1              BRGR1=0x02;
  42   1              BRGCON =0x03; //使能BRG  
  43   1      
  44   1              TR0=0;
  45   1              ET0=0;
  46   1              TR1=0;
  47   1              ET1=0;
  48   1      
  49   1              CLR=0;
  50   1              P0=0x03;        
  51   1              //EN=0;
  52   1      
  53   1              DEECON=0x00;
  54   1      
  55   1      }
C51 COMPILER V7.10   INT                                                                   06/18/2007 11:05:53 PAGE 2   

  56          void CCU_init(DWORD pwm)
  57          {
  58   1              
  59   1              OCB=1;                  // enable ports P1.6 PWM outputs
  60   1              TPCR2H=0x00;    // set CCU Prescaler:
  61   1              TPCR2L=0x31;    // divide by 100 (99+1)
  62   1                                              
  63   1              TCR21=0x04;             // Prescaler for Phase Locked Loop:
  64   1                                              // Input frequency must be in range of 0.5-1Mhz
  65   1                                              // InpFrq=PCLK/(PLLDIV+1)=(CCLK/2)/(PLLDIV+1)
  66   1                                              // using the internal RC oscillator: CCLK=7.373MHz 
  67   1                                              //              PLLDiv=6, 6+1=7      => 0.526 MHz
  68   1                                              // using Crystal 11.0592 MHz => 0.789 MHz
  69   1      
  70   1              CCCRB=0x01;             // non-inverted PWM output on channel B
  71   1      //      CCCRD=0x02;             // inverted PWM output on channel D
  72   1              
  73   1              TCR20=0x80;             // Start PLL, OutputMode: stop
  74   1              OCB=1;                  // wait a machine cycle
  75   1              while(PLLEN==0);// wait until PLL  locked
  76   1      
  77   1              TOR2H=0x00;             // Reload Value 0x00FF=255      
  78   1              TOR2L=0xff;             // -> PWM period
  79   1              TCR21|=0x80;    // update reload value
  80   1      
  81   1              OCRBH=(pwm&0x300)>>8;
  82   1              OCRBL=pwm&0xff;
  83   1      //      OCRBH=0x00;             // initialize Duty-Cycle channel A 0x0100 => 25%
  84   1      //      OCRBL=EEPROM_R(CONTRAST);
  85   1      //      OCRBL=0x01;             
  86   1              TCR21|=0x80;    // update duty cycle
  87   1      
  88   1      //      OCRDH=0x00;             // initialize Duty-Cycle channel D 0x0100 => 25%
  89   1      //      OCRDL=0x0F;                     
  90   1      //      TCR21|=0x80;    // update duty cycle
  91   1      
  92   1              TCR20=0x82;             // Set output mode: asymmetrical PWM 
  93   1      
  94   1      }
  95          
  96          void delay(BYTE x)
  97          {
  98   1              BYTE i,j,k;
  99   1              for(i=0;i<x;i++)
 100   1              {
 101   2                      for(j=0;j<200;j++)
 102   2                      {
 103   3                              for(k=0;k<50;k++)
 104   3                              {
 105   4                                      _nop_();
 106   4                              }
 107   3                      }
 108   2              }
 109   1      
 110   1      }
 111          BYTE EEPROM_R(WORD addr)
 112          {
 113   1              BYTE i,addr1;
 114   1              EA=0;
 115   1              DEECON=0;
 116   1              if(addr>0xff)
 117   1              {
C51 COMPILER V7.10   INT                                                                   06/18/2007 11:05:53 PAGE 3   

 118   2                      DEECON|=0x01;   
 119   2                      addr1=addr%0xff;
 120   2              }
 121   1              else
 122   1              {
 123   2                      DEECON&=0xfe;
 124   2                      addr1=addr;
 125   2              }
 126   1              DEEADR=addr1;
 127   1              while((DEECON&0x80)==0);
 128   1              i=DEEDAT;
 129   1              DEECON=0;
 130   1              EA=1;
 131   1              return i;
 132   1      }
 133          
 134          void EEPROM_W(WORD addr,BYTE dat)
 135          {
 136   1              BYTE addr1;
 137   1              EA = 0;
 138   1              DEECON = 0;
 139   1              if(addr>0xff)  //高八位地址
 140   1              {
 141   2                      DEECON |= 0x01; 
 142   2                      addr1 = addr%0xff;
 143   2              }
 144   1              else
 145   1              {
 146   2                      DEECON &= 0xfe;
 147   2                      addr1 = addr;
 148   2              }
 149   1              DEEDAT = dat;
 150   1              DEEADR = addr1;
 151   1              while((DEECON&0x80)==0);
 152   1              DEECON&=0x7f;//清零数据EEPROM 中断标志
 153   1              EA = 1;
 154   1      }


MODULE INFORMATION:   STATIC OVERLAYABLE
   CODE SIZE        =    264    ----
   CONSTANT SIZE    =   ----    ----
   XDATA SIZE       =   ----    ----
   PDATA SIZE       =   ----    ----
   DATA SIZE        =      2       7
   IDATA SIZE       =   ----    ----
   BIT SIZE         =   ----    ----
END OF MODULE INFORMATION.


C51 COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)