cmi_coder.tan.rpt

cmi encoder and decoder ok in Quartus ii 5.1

; Slack ; Required tsu ; Actual tsu ; From ; To   ; To Clock ;
+-------+--------------+------------+------+------+----------+
; N/A   ; None         ; 1.000 ns   ; cmi  ; t[0] ; clk      ;
; N/A   ; None         ; 1.000 ns   ; cmi  ; t[1] ; clk      ;
+-------+--------------+------------+------+------+----------+


+-----------------------------------------------------------------+
; tco                                                             ;
+-------+--------------+------------+----------+-----+------------+
; Slack ; Required tco ; Actual tco ; From     ; To  ; From Clock ;
+-------+--------------+------------+----------+-----+------------+
; N/A   ; None         ; 10.400 ns  ; nrz~reg0 ; nrz ; clk        ;
+-------+--------------+------------+----------+-----+------------+


+------------------------------------------------------------------+
; th                                                               ;
+---------------+-------------+-----------+------+------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To   ; To Clock ;
+---------------+-------------+-----------+------+------+----------+
; N/A           ; None        ; 0.900 ns  ; cmi  ; t[0] ; clk      ;
; N/A           ; None        ; 0.900 ns  ; cmi  ; t[1] ; clk      ;
+---------------+-------------+-----------+------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Fri Jun 08 01:28:58 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cmi_coder -c cmi_coder
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 200.0 MHz between source register "t[2]" and destination register "nrz~reg0"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C4; Fanout = 1; REG Node = 't[2]'
            Info: 2: + IC(0.300 ns) + CELL(1.000 ns) = 1.300 ns; Loc. = LC2_C4; Fanout = 1; REG Node = 'nrz~reg0'
            Info: Total cell delay = 1.000 ns ( 76.92 % )
            Info: Total interconnect delay = 0.300 ns ( 23.08 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.400 ns
                Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_C4; Fanout = 1; REG Node = 'nrz~reg0'
                Info: Total cell delay = 2.000 ns ( 83.33 % )
                Info: Total interconnect delay = 0.400 ns ( 16.67 % )
            Info: - Longest clock path from clock "clk" to source register is 2.400 ns
                Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_C4; Fanout = 1; REG Node = 't[2]'
                Info: Total cell delay = 2.000 ns ( 83.33 % )
                Info: Total interconnect delay = 0.400 ns ( 16.67 % )
        Info: + Micro clock to output delay of source is 0.500 ns
        Info: + Micro setup delay of destination is 0.600 ns
        Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: tsu for register "t[0]" (data pin = "cmi", clock pin = "clk") is 1.000 ns
    Info: + Longest pin to register delay is 2.800 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_91; Fanout = 2; PIN Node = 'cmi'
        Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.800 ns; Loc. = LC3_C4; Fanout = 1; REG Node = 't[0]'
        Info: Total cell delay = 2.800 ns ( 100.00 % )
    Info: + Micro setup delay of destination is 0.600 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_C4; Fanout = 1; REG Node = 't[0]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
Info: tco from clock "clk" to destination pin "nrz" through register "nrz~reg0" is 10.400 ns
    Info: + Longest clock path from clock "clk" to source register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_C4; Fanout = 1; REG Node = 'nrz~reg0'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Longest register to pin delay is 7.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_C4; Fanout = 1; REG Node = 'nrz~reg0'
        Info: 2: + IC(1.200 ns) + CELL(6.300 ns) = 7.500 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'nrz'
        Info: Total cell delay = 6.300 ns ( 84.00 % )
        Info: Total interconnect delay = 1.200 ns ( 16.00 % )
Info: th for register "t[0]" (data pin = "cmi", clock pin = "clk") is 0.900 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_C4; Fanout = 1; REG Node = 't[0]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro hold delay of destination is 1.300 ns
    Info: - Shortest pin to register delay is 2.800 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_91; Fanout = 2; PIN Node = 'cmi'
        Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.800 ns; Loc. = LC3_C4; Fanout = 1; REG Node = 't[0]'
        Info: Total cell delay = 2.800 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Jun 08 01:28:59 2007
    Info: Elapsed time: 00:00:02