cmi_coder.tan.qmsg

cmi encoder and decoder ok in Quartus ii 5.1

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register t\[2\] nrz~reg0 200.0 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 200.0 MHz between source register \"t\[2\]\" and destination register \"nrz~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.300 ns + Longest register register " "Info: + Longest register to register delay is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns t\[2\] 1 REG LC1_C4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C4; Fanout = 1; REG Node = 't\[2\]'" {  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "" { t[2] } "NODE_NAME" } "" } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.000 ns) 1.300 ns nrz~reg0 2 REG LC2_C4 1 " "Info: 2: + IC(0.300 ns) + CELL(1.000 ns) = 1.300 ns; Loc. = LC2_C4; Fanout = 1; REG Node = 'nrz~reg0'" {  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "1.300 ns" { t[2] nrz~reg0 } "NODE_NAME" } "" } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.000 ns ( 76.92 % ) " "Info: Total cell delay = 1.000 ns ( 76.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns ( 23.08 % ) " "Info: Total interconnect delay = 0.300 ns ( 23.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "1.300 ns" { t[2] nrz~reg0 } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { t[2] nrz~reg0 } { 0.000ns 0.300ns } { 0.000ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_39 4 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'" {  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "" { clk } "NODE_NAME" } "" } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns nrz~reg0 2 REG LC2_C4 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_C4; Fanout = 1; REG Node = 'nrz~reg0'" {  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "0.400 ns" { clk nrz~reg0 } "NODE_NAME" } "" } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "2.400 ns" { clk nrz~reg0 } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out nrz~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_39 4 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'" {  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "" { clk } "NODE_NAME" } "" } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns t\[2\] 2 REG LC1_C4 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_C4; Fanout = 1; REG Node = 't\[2\]'" {  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "0.400 ns" { clk t[2] } "NODE_NAME" } "" } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "2.400 ns" { clk t[2] } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out t[2] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "2.400 ns" { clk nrz~reg0 } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out nrz~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "2.400 ns" { clk t[2] } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out t[2] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 10 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 16 -1 0 } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 10 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "1.300 ns" { t[2] nrz~reg0 } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "1.300 ns" { t[2] nrz~reg0 } { 0.000ns 0.300ns } { 0.000ns 1.000ns } } } { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "2.400 ns" { clk nrz~reg0 } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out nrz~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "2.400 ns" { clk t[2] } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out t[2] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "" { nrz~reg0 } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { nrz~reg0 } {  } {  } } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 10 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "t\[0\] cmi clk 1.000 ns register " "Info: tsu for register \"t\[0\]\" (data pin = \"cmi\", clock pin = \"clk\") is 1.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.800 ns + Longest pin register " "Info: + Longest pin to register delay is 2.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns cmi 1 PIN PIN_91 2 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_91; Fanout = 2; PIN Node = 'cmi'" {  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "" { cmi } "NODE_NAME" } "" } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.800 ns t\[0\] 2 REG LC3_C4 1 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.800 ns; Loc. = LC3_C4; Fanout = 1; REG Node = 't\[0\]'" {  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "0.800 ns" { cmi t[0] } "NODE_NAME" } "" } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 100.00 % ) " "Info: Total cell delay = 2.800 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "2.800 ns" { cmi t[0] } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "2.800 ns" { cmi cmi~out t[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.000ns 0.800ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_39 4 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'" {  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "" { clk } "NODE_NAME" } "" } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns t\[0\] 2 REG LC3_C4 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_C4; Fanout = 1; REG Node = 't\[0\]'" {  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "0.400 ns" { clk t[0] } "NODE_NAME" } "" } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "2.400 ns" { clk t[0] } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out t[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "2.800 ns" { cmi t[0] } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "2.800 ns" { cmi cmi~out t[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.000ns 0.800ns } } } { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "2.400 ns" { clk t[0] } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out t[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk nrz nrz~reg0 10.400 ns register " "Info: tco from clock \"clk\" to destination pin \"nrz\" through register \"nrz~reg0\" is 10.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_39 4 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'" {  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "" { clk } "NODE_NAME" } "" } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns nrz~reg0 2 REG LC2_C4 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_C4; Fanout = 1; REG Node = 'nrz~reg0'" {  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "0.400 ns" { clk nrz~reg0 } "NODE_NAME" } "" } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "2.400 ns" { clk nrz~reg0 } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out nrz~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 10 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.500 ns + Longest register pin " "Info: + Longest register to pin delay is 7.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns nrz~reg0 1 REG LC2_C4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_C4; Fanout = 1; REG Node = 'nrz~reg0'" {  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "" { nrz~reg0 } "NODE_NAME" } "" } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(6.300 ns) 7.500 ns nrz 2 PIN PIN_57 0 " "Info: 2: + IC(1.200 ns) + CELL(6.300 ns) = 7.500 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'nrz'" {  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "7.500 ns" { nrz~reg0 nrz } "NODE_NAME" } "" } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns ( 84.00 % ) " "Info: Total cell delay = 6.300 ns ( 84.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 16.00 % ) " "Info: Total interconnect delay = 1.200 ns ( 16.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "7.500 ns" { nrz~reg0 nrz } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "7.500 ns" { nrz~reg0 nrz } { 0.000ns 1.200ns } { 0.000ns 6.300ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "2.400 ns" { clk nrz~reg0 } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out nrz~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "7.500 ns" { nrz~reg0 nrz } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "7.500 ns" { nrz~reg0 nrz } { 0.000ns 1.200ns } { 0.000ns 6.300ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "t\[0\] cmi clk 0.900 ns register " "Info: th for register \"t\[0\]\" (data pin = \"cmi\", clock pin = \"clk\") is 0.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_39 4 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'" {  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "" { clk } "NODE_NAME" } "" } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns t\[0\] 2 REG LC3_C4 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_C4; Fanout = 1; REG Node = 't\[0\]'" {  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "0.400 ns" { clk t[0] } "NODE_NAME" } "" } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "2.400 ns" { clk t[0] } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out t[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 16 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.800 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns cmi 1 PIN PIN_91 2 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_91; Fanout = 2; PIN Node = 'cmi'" {  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "" { cmi } "NODE_NAME" } "" } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.800 ns t\[0\] 2 REG LC3_C4 1 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.800 ns; Loc. = LC3_C4; Fanout = 1; REG Node = 't\[0\]'" {  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "0.800 ns" { cmi t[0] } "NODE_NAME" } "" } } { "cmi_de.v" "" { Text "H:/cmi/cmi_de.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 100.00 % ) " "Info: Total cell delay = 2.800 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "2.800 ns" { cmi t[0] } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "2.800 ns" { cmi cmi~out t[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.000ns 0.800ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "2.400 ns" { clk t[0] } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out t[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "g:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "g:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "cmi_coder" "UNKNOWN" "V1" "H:/cmi/db/cmi_coder.quartus_db" { Floorplan "H:/cmi/" "" "2.800 ns" { cmi t[0] } "NODE_NAME" } "" } } { "g:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/altera/quartus51/bin/Technology_Viewer.qrui" "2.800 ns" { cmi cmi~out t[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.000ns 0.800ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 08 01:28:59 2007 " "Info: Processing ended: Fri Jun 08 01:28:59 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}