decoder.rpt

cmi encoder and decoder ok in Quartus ii 5.1

Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                h:\cmi\decoder.rpt
decoder

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                               Logic cells placed in LAB 'B'
        +--------------------- LC17 clk_idv
        | +------------------- LC18 cmi
        | | +----------------- LC26 nrz_in
        | | | +--------------- LC25 nrz_out
        | | | | +------------- LC24 :1
        | | | | | +----------- LC23 :2
        | | | | | | +--------- LC22 :3
        | | | | | | | +------- LC21 :30
        | | | | | | | | +----- LC20 |74163:25|p74163:sub|QA
        | | | | | | | | | +--- LC19 |74163:25|p74163:sub|QB
        | | | | | | | | | | +- LC27 |74163:25|p74163:sub|QC
        | | | | | | | | | | | 
        | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC17 -> * * - * * * * * * * * | - * | <-- clk_idv
LC18 -> - - - - * - * - - - - | - * | <-- cmi
LC24 -> - - - - - * - - - - - | - * | <-- :1
LC23 -> - - - * - - - - - - - | - * | <-- :2
LC22 -> - - - * - - - - - - - | - * | <-- :3
LC21 -> - * - - - - - * - - - | - * | <-- :30
LC20 -> - * * - - - - * * * * | - * | <-- |74163:25|p74163:sub|QA
LC19 -> - * * - - - - * - * * | - * | <-- |74163:25|p74163:sub|QB
LC27 -> - * * - - - - * * * * | - * | <-- |74163:25|p74163:sub|QC

Pin
43   -> - - - - - - - - - - - | - - | <-- clk


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                h:\cmi\decoder.rpt
decoder

** EQUATIONS **

clk      : INPUT;

-- Node name is 'clk_idv' = ':32' 
-- Equation name is 'clk_idv', type is output 
 clk_idv = TFFE( VCC, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is 'cmi' = ':31' 
-- Equation name is 'cmi', type is output 
 cmi     = DFFE( _EQ001 $  _LC021, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 =  clk_idv &  _LC021 &  _LC027 &  _X001
         #  clk_idv & !_LC019 & !_LC020 &  _LC021
         # !clk_idv & !_LC021 &  _LC027 &  _X001
         # !clk_idv & !_LC019 & !_LC020 & !_LC021;
  _X001  = EXP( _LC019 &  _LC020);

-- Node name is 'nrz_in' 
-- Equation name is 'nrz_in', location is LC026, type is output.
 nrz_in  = LCELL( _EQ002 $  _LC020);
  _EQ002 = !_LC019 &  _LC020 &  _LC027
         #  _LC019 & !_LC020 & !_LC027;

-- Node name is 'nrz_out' = ':4' 
-- Equation name is 'nrz_out', type is output 
 nrz_out = DFFE(!_LC023 $  _LC022,  clk_idv,  VCC,  VCC,  VCC);

-- Node name is '|74163:25|p74163:sub|:34' = '|74163:25|p74163:sub|QA' 
-- Equation name is '_LC020', type is buried 
_LC020   = DFFE( _EQ003 $ !_LC027,  clk_idv,  VCC,  VCC,  VCC);
  _EQ003 =  _LC020 & !_LC027;

-- Node name is '|74163:25|p74163:sub|:35' = '|74163:25|p74163:sub|QB' 
-- Equation name is '_LC019', type is buried 
_LC019   = DFFE( _EQ004 $  GND,  clk_idv,  VCC,  VCC,  VCC);
  _EQ004 =  _LC019 & !_LC020 & !_LC027
         # !_LC019 &  _LC020 & !_LC027;

-- Node name is '|74163:25|p74163:sub|:36' = '|74163:25|p74163:sub|QC' 
-- Equation name is '_LC027', type is buried 
_LC027   = DFFE( _EQ005 $  GND,  clk_idv,  VCC,  VCC,  VCC);
  _EQ005 =  _LC019 &  _LC020 & !_LC027;

-- Node name is ':1' 
-- Equation name is '_LC024', type is buried 
_LC024   = DFFE( cmi $  GND, !clk_idv,  VCC,  VCC,  VCC);

-- Node name is ':2' 
-- Equation name is '_LC023', type is buried 
_LC023   = DFFE( _LC024 $  GND,  clk_idv,  VCC,  VCC,  VCC);

-- Node name is ':3' 
-- Equation name is '_LC022', type is buried 
_LC022   = DFFE( cmi $  GND,  clk_idv,  VCC,  VCC,  VCC);

-- Node name is ':30' 
-- Equation name is '_LC021', type is buried 
_LC021   = TFFE( VCC,  _EQ006,  VCC,  VCC,  VCC);
  _EQ006 =  _X002 &  _X003 &  _X004;
  _X002  = EXP(!clk_idv & !_LC019 &  _LC020 & !_LC027);
  _X003  = EXP(!clk_idv &  _LC019 & !_LC020 & !_LC027);
  _X004  = EXP(!clk_idv &  _LC019 &  _LC020);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                         h:\cmi\decoder.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 2,755K