cmi_de.v

来自「cmi encoder and decoder ok in Quartus」· Verilog 代码 · 共 19 行

module cmi_coder(cmi,clk,nrz);
	input clk,cmi;
	output nrz;
	reg nrz;
	reg t[3:0];
	always @ (negedge clk)
	 begin
	 t[1]<=cmi;
     nrz<=t[3];
	 end
	
	always @ (posedge clk)
		begin
		t[0]<=cmi;
		t[2]<=t[1];
		end
	   xnor(t[3],t[0],t[2]);
	endmodule