encoder.v

来自「cmi encoder and decoder ok in Quartus」· Verilog 代码 · 共 37 行

module encoder (clk,clkt,nrz,rst,cmi);
input clk,nrz,clkt,rst;
output cmi;
reg cmi;
reg t,j;
reg [1:0] out;
initial
	begin
	t<=0;
	j<=1;
	end
always @ (posedge clkt)
    begin
    if(rst) out<=2'b00;
    else if(nrz==0) out<=2'b01;
    else if(t) 
          begin
	      out<=2'b11;t<=0;
          end
         else 
		  begin
          out<=2'b00;t<=1;
	      end
    end
always @ (posedge clk)
	begin
	if (j)
	 begin
	 cmi<=out[1];j<=0;
	 end
	else
	 begin
	 cmi<=out[0];j<=1;
	 end
	end
endmodule