div.v

来自「cmi encoder and decoder ok in Quartus」· Verilog 代码 · 共 17 行

module div(clk,clk_div);
input clk;
output clk_div;
reg clk_div;
reg t;
initial
begin
clk_div<=0;
t=1;
end
always @ (posedge clk)
 begin
 	clk_div=~clk_div;
 end
endmodule