📄 cmi_coder.fit.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--A1L5Q is nrz~reg0 at LC2_C4
--operation mode is normal
A1L5Q_lut_out = t[2] $ !t[0];
A1L5Q = DFFEA(A1L5Q_lut_out, !GLOBAL(clk), , , , , );
--A1L4Q is nrz~0 at LC2_C4
--operation mode is normal
A1L4Q = A1L5Q;
--t[2] is t[2] at LC1_C4
--operation mode is normal
t[2]_lut_out = t[1];
t[2] = DFFEA(t[2]_lut_out, GLOBAL(clk), , , , , );
--A1L12Q is t[2]~3 at LC1_C4
--operation mode is normal
A1L12Q = t[2];
--t[0] is t[0] at LC3_C4
--operation mode is normal
t[0]_lut_out = cmi;
t[0] = DFFEA(t[0]_lut_out, GLOBAL(clk), , , , , );
--A1L8Q is t[0]~4 at LC3_C4
--operation mode is normal
A1L8Q = t[0];
--t[1] is t[1] at LC4_C4
--operation mode is normal
t[1]_lut_out = cmi;
t[1] = DFFEA(t[1]_lut_out, !GLOBAL(clk), , , , , );
--A1L10Q is t[1]~5 at LC4_C4
--operation mode is normal
A1L10Q = t[1];
--clk is clk at PIN_39
--operation mode is input
clk = INPUT();
--cmi is cmi at PIN_91
--operation mode is input
cmi = INPUT();
--nrz is nrz at PIN_57
--operation mode is output
nrz = OUTPUT(A1L5Q);
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