usbohci.bak

来自「RDC R2886 USB Ehci ohc测试源码,paradigm c++上」· BAK 代码 · 共 250 行

// USB Host Controller test pattern include file
// Modification List:
// 05/19/2003    Jeff

/* ED info field */
#define ED_FA_0		0x0000
#define ED_FA_3		0x0003
#define ED_EN_0		0x0000
#define ED_EN_1		0x0080
#define ED_EN_2		0x0100
#define ED_EN_3		0x0180
#define ED_D_TD		0x0000
#define ED_D_OUT	0x0800
#define ED_D_IN		0x1000
#define ED_S		0x2000
#define ED_K		0x4000
#define ED_F		0x8000

/* ED States */
#define ED_NEW 		0x00
#define ED_UNLINK 	0x01
#define ED_OPER		0x02
#define ED_DEL		0x04
#define ED_URB_DEL  	0x08

/* usb_ohci_ed */
typedef __far struct ohci_ed_t {
	u32 hwINFO;       
	u32 hwTailP;
	u32 hwHeadP;
	u32 hwNextED;

	struct ed * ed_prev;  
	u8 int_period;
	u8 int_branch;
	u8 int_load; 
	u8 int_interval;
	u8 state;
	u8 type; 
	u16 last_iso;
	struct ed * ed_rm_list;
	
	u32 unused[1];
}ohci_ed_t;

typedef __far struct int_data_buf {
   u32 data;
}int_data_buf;
/* TD info field */
#define TD_CC       0xf0000000L
#define TD_EC       0x0C000000L
#define TD_T_DATA0  0x02000000L
#define TD_T_DATA1  0x03000000L
#define TD_T_ED	    0x00000000L
#define TD_DI       0x00400000L
#define TD_DP_SETUP 0x00000000L
#define TD_DP_OUT   0x00080000L
#define TD_DP_IN    0x00100000L
#define TD_R        0x00040000L

#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffffL) | (((cc) & 0x0f) << 28)
#define TD_T        0x03000000L
#define TD_T_TOGGLE 0x00000000L
#define TD_DI_SET(X) (((X) & 0x07)<< 21)
#define TD_DP       0x00180000L

#define TD_ISO	    0x00010000L
#define TD_DEL      0x00020000L

/* CC Codes */
#define TD_CC_NOERROR      0x000000000L
#define TD_CC_CRC          0x010000000L
#define TD_CC_BITSTUFFING  0x020000000L
#define TD_CC_DATATOGGLEM  0x030000000L
#define TD_CC_STALL        0x040000000L
#define TD_DEVNOTRESP      0x050000000L
#define TD_PIDCHECKFAIL    0x060000000L
#define TD_UNEXPECTEDPID   0x070000000L
#define TD_DATAOVERRUN     0x080000000L
#define TD_DATAUNDERRUN    0x090000000L
#define TD_BUFFEROVERRUN   0x0C0000000L
#define TD_BUFFERUNDERRUN  0x0D0000000L
#define TD_NOTACCESSED     0x0F0000000L

#define MAXPSW 1
typedef __far struct ohci_td_t {
	u32 hwINFO;
  	u32 hwCBP;		/* Current Buffer Pointer */
  	u32 hwNextTD;		/* Next TD Pointer */
  	u32 hwBE;		/* Memory Buffer End Pointer */

  	u16 hwPSW[MAXPSW];
  	u8 unused;
  	u8 index;
  	struct ed * ed;
  	struct td * next_dl_td;
  	struct urb * urb;

	u16 unused2[3];
}ohci_td_t;	/* normally 16, iso needs 32 */

//isochronous transfer descriptor
#define MAXBufSize	1024
typedef __far struct ohci_itd {
   u32 hwINFO;
  	u32 hwCBP;		/* Current Buffer Pointer */
  	u32 hwNextTD;		/* Next TD Pointer */
  	u32 hwBE;		/* Memory Buffer End Pointer */

  	u16 hwPSW[8];
}ohci_itd;

typedef __far struct iso_data{
	char	data[4096];
}iso_data;
/*
 * HcControl (control) register masks
 */
#define OHCI_CTRL_CBSR	(3 << 0)	/* control/bulk service ratio */
#define OHCI_CTRL_PLE	(1 << 2)	/* periodic list enable */
#define OHCI_CTRL_IE	(1 << 3)	/* isochronous enable */
#define OHCI_CTRL_CLE	(1 << 4)	/* control list enable */
#define OHCI_CTRL_BLE	(1 << 5)	/* bulk list enable */
#define OHCI_CTRL_HCFS	(3 << 6)	/* host controller functional state */
#define OHCI_CTRL_IR	(1 << 8)	/* interrupt routing */
#define OHCI_CTRL_RWC	(1 << 9)	/* remote wakeup connected */
#define OHCI_CTRL_RWE	(1 << 10)	/* remote wakeup enable */

/* pre-shifted values for HCFS */
#define OHCI_USB_RESET		(0 << 6)
#define OHCI_USB_RESUME		(1 << 6)
#define OHCI_USB_OPER		(2 << 6)
#define OHCI_USB_SUSPEND	(3 << 6)

/*
 * HcCommandStatus (cmdstatus) register masks
 */
#define OHCI_HCR	(1 << 0)	/* host controller reset */
#define OHCI_CLF  	(1 << 1)	/* control list filled */
#define OHCI_BLF  	(1 << 2)	/* bulk list filled */
#define OHCI_OCR  	(1 << 3)	/* ownership change request */
#define OHCI_SOC  	0x30000L	/* scheduling overrun count */

/*
 * masks used with interrupt registers:
 * HcInterruptStatus (intrstatus)
 * HcInterruptEnable (intrenable)
 * HcInterruptDisable (intrdisable)
 */
#define OHCI_INTR_SO	(1 << 0)	/* scheduling overrun */
#define OHCI_INTR_WDH	(1 << 1)	/* writeback of done_head */
#define OHCI_INTR_SF	(1 << 2)	/* start frame */
#define OHCI_INTR_RD	(1 << 3)	/* resume detect */
#define OHCI_INTR_UE	(1 << 4)	/* unrecoverable error */
#define OHCI_INTR_FNO	(1 << 5)	/* frame number overflow */
#define OHCI_INTR_RHSC	(1 << 6)	/* root hub status change */
#define OHCI_INTR_OC	0x40000000L	/* ownership change */
#define OHCI_INTR_MIE	0x80000000L	/* master interrupt enable */


/* OHCI ROOT HUB REGISTER MASKS */
 
/* roothub.portstatus [i] bits */
#define RH_PS_CCS            0x00000001L   	/* current connect status */
#define RH_PS_PES            0x00000002L   	/* port enable status*/
#define RH_PS_PSS            0x00000004L   	/* port suspend status */
#define RH_PS_POCI           0x00000008L   	/* port over current indicator */
#define RH_PS_PRS            0x00000010L  	/* port reset status */
#define RH_PS_PPS            0x00000100L   	/* port power status */
#define RH_PS_LSDA           0x00000200L    	/* low speed device attached */
#define RH_PS_CSC            0x00010000L 	/* connect status change */
#define RH_PS_PESC           0x00020000L   	/* port enable status change */
#define RH_PS_PSSC           0x00040000L    	/* port suspend status change */
#define RH_PS_OCIC           0x00080000L    	/* over current indicator change */
#define RH_PS_PRSC           0x00100000L   	/* port reset status change */

/* roothub.status bits */
#define RH_HS_LPS	     0x00000001L		/* local power status */
#define RH_HS_OCI	     0x00000002L		/* over current indicator */
#define RH_HS_DRWE	     0x00008000L		/* device remote wakeup enable */
#define RH_HS_LPSC	     0x00010000L		/* local power status change */
#define RH_HS_OCIC	     0x00020000L		/* over current indicator change */
#define RH_HS_CRWE	     0x80000000L		/* clear remote wakeup enable */

/* roothub.b masks */
#define RH_B_DR		0x0000ffffL		/* device removable flags */
#define RH_B_PPCM	0xffff0000L		/* port power control mask */

/* roothub.a masks */
#define	RH_A_NDP	(0x02 << 0)		/* number of downstream ports */
#define	RH_A_PSM	(1 << 8)		/* power switching mode */
#define	RH_A_NPS	(1 << 9)		/* no power switching */
#define	RH_A_DT		(1 << 10)		/* device type (mbz) */
#define	RH_A_OCPM	(1 << 11)		/* over current protection mode */
#define	RH_A_NOCP	(1 << 12)		/* no over current protection */
#define	RH_A_POTPGT	0xFF000000L		/* power on to power good time */

/*
 * Port attach
 */
#define RH_Port1Attach	0x01
#define RH_Port2Attach	0x02

/*
 * Maximum number of root hub ports.  
 */
#define MAX_ROOT_PORTS	2	/* maximum OHCI root hub ports */

typedef __far struct ohci_registers {
	/* control and status registers */
	u32	revision;
	u32	control;
	u32	cmdstatus;
	u32	intrstatus;
	u32	intrenable;
	u32	intrdisable;
	/* memory pointers */
	u32	hcca;
	u32	ed_periodcurrent;
	u32	ed_controlhead;
	u32	ed_controlcurrent;
	u32	ed_bulkhead;
	u32	ed_bulkcurrent;
	u32	donehead;
	/* frame counters */
	u32	fminterval;
	u32	fmremaining;
	u32	fmnumber;
	u32	periodicstart;
	u32	lsthresh;
	/* Root hub ports */
	u32	a;
	u32	b;
	u32	status;
	u32	portstatus1;
	u32	portstatus2;
} ohci_registers;

#define NUM_INTS 32	/* part of the OHCI standard */
typedef __far struct ohci_hcca_desc {
	u32	int_table[NUM_INTS];	/* Interrupt ED table */
	u16	frame_no;		/* current frame number */
	u16	pad1;			/* set to 0 on each frame_no change */
	u32	done_head;		/* info returned for an interrupt */
	u8	reserved_for_hc[116];
}ohci_hcca_desc;

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